| 1. |
- Horga, Adrian, 1989-
(författare)
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Performance and Security Analysis for GPU-Based Applications
- 2022
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Graphics Processing Units (GPUs) are becoming more and more prevalent in general-purpose computing. GPUs are used in areas from embedded systems to super-computing. With applications ranging from fluid dynamics simulations to image processing, machine learning, and encryption, GPU programs need to satisfy not only performance requirements but also various other non-functional constraints. Besides the aspects regarding performance, also security and the worst case execution time (WCET) need to be considered for such GPU applications. In our work, we study such non-functional properties and present approaches to detect and solve issues regarding them.First, we focus on the performance of GPU applications by detecting cache related performance bottlenecks. We detect the root causes of such bottlenecks and provide solutions to reduce their negative impact on performance. We also discuss and compare the impact of cache replacement policies and thread scheduling policies on the performance of GPU applications.Then, we present a measurement-based technique, which combines symbolic execution and genetic algorithms, and is used for estimating the WCET of GPU programs. Our proposed technique helps to produce test inputs that lead towards the WCET of a program. We also propose solutions to alleviate the inherent complexity of GPU programs due to branching behavior and high number of threads running in parallel.In continuation, we propose a technique to expose the side-channel leakage of shared memory in GPU implementations of cryptographic algorithms. We evaluate the robustness of such algorithms in the context of shared memory side-channel leakage. Also, we discuss the security and side-channel leakage for different implementations of the same algorithm.Finally, a formal approach is presented for the detection of GPU shared memory bank conflicts. We explore and discuss the impact of such conflicts on the performance and security of GPU applications. We show how our approach can help in producing inputs that can lead towards the WCET. We also discuss how our approach can be used to evaluate the leakage of the shared memory side-channel for GPU implementations of cryptographic algorithms.
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| 2. |
- Ganjei, Zeinab, 1989-
(författare)
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Parameterized Verification of Synchronized Concurrent Programs
- 2021
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- There is currently an increasing demand for concurrent programs. Checking the correctness of concurrent programs is a complex task due to the interleavings of processes. Sometimes, violation of the correctness properties in such systems causes human or resource losses; therefore, it is crucial to check the correctness of such systems. Two main approaches to software analysis are testing and formal verification. Testing can help discover many bugs at a low cost. However, it cannot prove the correctness of a program. Formal verification, on the other hand, is the approach for proving program correctness. Model checking is a formal verification technique that is suitable for concurrent programs. It aims to automatically establish the correctness (expressed in terms of temporal properties) of a program through an exhaustive search of the behavior of the system. Model checking was initially introduced for the purpose of verifying finite‐state concurrent programs, and extending it to infinite‐state systems is an active research area.In this thesis, we focus on the formal verification of parameterized systems. That is, systems in which the number of executing processes is not bounded a priori. We provide fully-automatic and parameterized model checking techniques for establishing the correctness of safety properties for certain classes of concurrent programs. We provide an open‐source prototype for every technique and present our experimental results on several benchmarks.First, we address the problem of automatically checking safety properties for bounded as well as parameterized phaser programs. Phaser programs are concurrent programs that make use of the complex synchronization construct of Habanero Java phasers. For the bounded case, we establish the decidability of checking the violation of program assertions and the undecidability of checking deadlock‐freedom. For the parameterized case, we study different formulations of the verification problem and propose an exact procedure that is guaranteed to terminate for some reachability problems even in the presence of unbounded phases and arbitrarily many spawned processes. Second, we propose an approach for automatic verification of parameterized concurrent programs in which shared variables are manipulated by atomic transitions to count and synchronize the spawned processes. For this purpose, we introduce counting predicates that related counters that refer to the number of processes satisfying some given properties to the variables that are directly manipulated by the concurrent processes. We then combine existing works on the counter, predicate, and constrained monotonic abstraction and build a nested counterexample‐based refinement scheme to establish correctness. Third, we introduce Lazy Constrained Monotonic Abstraction for more efficient exploration of well‐structured abstractions of infinite‐state non‐monotonic systems. We propose several heuristics and assess the efficiency of the proposed technique by extensive experiments using our open‐source prototype. Lastly, we propose a sound but (in general) incomplete procedure for automatic verification of safety properties for a class of fault‐tolerant distributed protocols described in the Heard‐Of (HO for short) model. The HO model is a popular model for describing distributed protocols. We propose a verification procedure that is guaranteed to terminate even for unbounded number of the processes that execute the distributed protocol.
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| 3. |
- Zhou, Yuanbin, 1991-
(författare)
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Synthesis of Safety-Critical Real-Time Systems
- 2022
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Modern safety-critical real-time systems are becoming more and more complex, due to sophisticated applications such as advanced driving assistance, automated driving, advanced infotainment, and applications involving machine learning and deep learning. This has led to increased requirements for the communication infrastructures. Real-time bus-based communication techniques, such as CAN and FlexRay, have been widely adopted for decades, due to their low cost and reliable communication capability. However, the bandwidth provided by these technologies is often not enough for modern safety-critical systems. Time-Sensitive Networking (TSN) is a promising technique that can handle the increasing bandwidth requirements, while meeting real-time constraints and providing Ethernet compatible solutions. We have studied the synthesis of schedules and routes for TSN, in order to fulfill timing and reliability requirements for safety-critical systems. Functional safety is an important goal for such systems, to ensure that no unreasonable risks are taken. This involves handling random and systematic faults, both of which are considered in this work. We synthesize schedules and routes for TSN so that the probability of faulty transmission due to random faults is below a certain threshold.ASIL Decomposition, introduced in the automotive industry, is applied to handle systematic faults, while achieving overall cost minimization. In order to improve schedulability, preemption support in TSN has also been studied. Heuristic algorithms are proposed for all the above contributions to address scalability issues characterized for the constrained synthesis and optimization problem addressed.Traditional designs for safety-critical systems usually deploy a federated architecture, where several processors are available and each processor implements one dedicated function. An important goal is to achieve fault containment. However, due to the increasing complexity of modern safety-critical systems, this architecture is no longer scalable. Therefore, several tasks with different criticality levels are usually integrated on the same computing platform. A key aspect for such systems is to achieve the required independence between tasks at different criticality levels and to guarantee that they do not interfere each other. We have developed a partitioned scheduling technique for mixed-criticality systems to achieve temporal independence, while minimizing the CPU usage.
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| 4. |
- Aghaee Ghaleshahi, Nima, 1980-
(författare)
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Thermal Issues in Testing of Advanced Systems on Chip
- 2015
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced.The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.
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| 5. |
- Aminifar, Amir, 1987-
(författare)
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Analysis, Design, and Optimization of Embedded Control Systems
- 2016
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Today, many embedded or cyber-physical systems, e.g., in the automotive domain, comprise several control applications, sharing the same platform. It is well known that such resource sharing leads to complex temporal behaviors that degrades the quality of control, and more importantly, may even jeopardize stability in the worst case, if not properly taken into account.In this thesis, we consider embedded control or cyber-physical systems, where several control applications share the same processing unit. The focus is on the control-scheduling co-design problem, where the controller and scheduling parameters are jointly optimized. The fundamental difference between control applications and traditional embedded applications motivates the need for novel methodologies for the design and optimization of embedded control systems. This thesis is one more step towards correct design and optimization of embedded control systems.Offline and online methodologies for embedded control systems are covered in this thesis. The importance of considering both the expected control performance and stability is discussed and a control-scheduling co-design methodology is proposed to optimize control performance while guaranteeing stability. Orthogonal to this, bandwidth-efficient stabilizing control servers are proposed, which support compositionality, isolation, and resource-efficiency in design and co-design. Finally, we extend the scope of the proposed approach to non-periodic control schemes and address the challenges in sharing the platform with self-triggered controllers. In addition to offline methodologies, a novel online scheduling policy to stabilize control applications is proposed.
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| 6. |
- Aysan, Hüseyin, 1982-
(författare)
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Fault-Tolerance Strategies and Probabilistic Guarantees for Real-Time Systems
- 2012
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Ubiquitous deployment of embedded systems is having a substantial impact on our society, since they interact with our lives in many critical real-time applications. Typically, embedded systems used in safety or mission critical applications (e.g., aerospace, avionics, automotive or nuclear domains) work in harsh environments where they are exposed to frequent transient faults such as power supply jitter, network noise and radiation. They are also susceptible to errors originating from design and production faults. Hence, they have the design objective to maintain the properties of timeliness and functional correctness even under error occurrences. Fault-tolerance plays a crucial role towards achieving dependability, and the fundamental requirement for the design of effective and efficient fault-tolerance mechanisms is a realistic and applicable model of potential faults and their manifestations. An important factor to be considered in this context is the random nature of faults and errors, which, if addressed in the timing analysis by assuming a rigid worst-case occurrence scenario, may lead to inaccurate results. It is also important that the power, weight, space and cost constraints of embedded systems are addressed by efficiently using the available resources for fault-tolerance. This thesis presents a framework for designing predictably dependable embedded real-time systems by jointly addressing the timeliness and the reliability properties. It proposes a spectrum of fault-tolerance strategies particularly targeting embedded real-time systems. Efficient resource usage is attained by considering the diverse criticality levels of the systems' building blocks. The fault-tolerance strategies are complemented with the proposed probabilistic schedulability analysis techniques, which are based on a comprehensive stochastic fault and error model.
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| 7. |
- Bao, Min, 1981-
(författare)
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System-Level Techniques for Temperature-Aware Energy Optimization
- 2010
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Energy consumption has become one of the main design constraints in today’s integrated circuits. Techniques for energy optimization, from circuit-level up to system-level, have been intensively researched.The advent of large-scale integration with deep sub-micron technologies has led to both high power densities and high chip working temperatures. At the same time, leakage power is becoming the dominant power consumption source of circuits, due to continuously lowered threshold voltages, as technology scales. In this context, temperature is an important parameter. One aspect, of particular interest for this thesis, is the strong inter-dependency between leakage and temperature. Apart from leakage power, temperature also has an important impact on circuit delay and, implicitly, on the frequency, mainly through its influence on carrier mobility and threshold voltage. For power-aware design techniques, temperature has become a major factor to be considered. In this thesis, we address the issue of system-level energy optimization for real-time embedded systems taking temperature aspects into consideration.We have investigated two problems in this thesis: (1) Energy optimization via temperature-aware dynamic voltage/frequency scaling (DVFS). (2) Energy optimization through temperature-aware idle time (or slack) distribution (ITD). For the above two problems, we have proposed off-line techniques where only static slack is considered. To further improve energy efficiency, we have also proposed online techniques, which make use of both static and dynamic slack. Experimental results have demonstrated that considerable improvement of the energy efficiency can be achieved by applying our temperature-aware optimization techniques. Another contribution of this thesis is an analytical temperature analysis approach which is both accurate and sufficiently fast to be used inside an energy optimization loop.
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| 8. |
- Bujosa Mateu, Daniel
(författare)
-
Enhancing TSN Adoption by Industry : Tools to Support Migrating Ethernet-based Legacy Networks into TSN
- 2023
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- New technologies present opportunities and challenges for industries. One major challenge is the ease, or even feasibility, of its adoption. The Time-Sensitive Networking (TSN) standards offer a range of features relevant to various applications and are key for the transition to Industry 4.0. These features include deterministic zero-jitter, low-latency data transmission, transmission of traffic with various levels of time-criticality on the same network, fault tolerance mechanisms, and advanced network management allowing dynamic reconfiguration.This thesis aims to develop tools that enable the industry to adopt TSN easily and efficiently. Specifically, we create tools that facilitate the migration of legacy networks to TSN, enabling the preservation of most of the legacy systems and solutions while reducing costs and adoption time. Firstly, we introduce LETRA (Legacy Ethernet-based Traffic Mapping Tool), a tool for mapping Ethernet-based legacy traffic to the new TSN traffic classes. Secondly, we develop HERMES (Heuristic Multi-queue Scheduler), a heuristic Time-Triggered (TT) traffic scheduler that can meet the characteristics of legacy systems and provide quick results suitable for reconfiguration. Thirdly, we develop TALESS (TSN with Legacy End-Stations Synchronization), a mechanism to avoid adverse consequences caused by the lack of synchronization between legacy systems and TSN-based ones, as not all legacy systems need to support the TSN synchronization mechanisms. Finally, we improve Stream Reservation Protocol (SRP) to enhance Audio-Video Bridging (AVB) traffic configuration in terms of termination and consistency.
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| 9. |
- He, Zhiyuan, 1976-
(författare)
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Temperature Aware and Defect-Probability Driven Test Scheduling for System-on-Chip
- 2010
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The high complexity of modern electronic systems has resulted in a substantial increase in the time-to-market as well as in the cost of design, production, and testing. Recently, in order to reduce the design cost, many electronic systems have employed a core-based system-on-chip (SoC) implementation technique, which integrates pre-defined and pre-verified intellectual property cores into a single silicon die. Accordingly, the testing of manufactured SoCs adopts a modular approach in which test patterns are generated for individual cores and are applied to the corresponding cores separately. Among many techniques that reduce the cost of modular SoC testing, test scheduling is widely adopted to reduce the test application time. This thesis addresses the problem of minimizing the test application time for modular SoC tests with considerations on three critical issues: high testing temperature, temperature-dependent failures, and defect probabilities.High temperature occurs in testing modern SoCs and it may cause damages to the cores under test. We address the temperature-aware test scheduling problem aiming to minimize the test application time and to avoid the temperature of the cores under test exceeding a certain limit. We have developed a test set partitioning and interleaving technique and a set of test scheduling algorithms to solve the addressed problem.Complicated temperature dependences and defect-induced parametric failures are more and more visible in SoCs manufactured with nanometer technology. In order to detect the temperature-dependent defects, a chip should be tested at different temperature levels. We address the SoC multi-temperature testing issue where tests are applied to a core only when the temperature of that core is within a given temperature interval. We have developed test scheduling algorithms for multi-temperature testing of SoCs.Volume production tests often employ an abort-on-first-fail (AOFF) approach which terminates the chip test as soon as the first fault is detected. Defect probabilities of individual cores in SoCs can be used to compute the expected test application time of modular SoC tests using the AOFF approach. We address the defect-probability driven SoC test scheduling problem aiming to minimize the expected test application time with a power constraint. We have proposed techniques which utilize the defect probability to generate efficient test schedules.Extensive experiments based on benchmark designs have been performed to demonstrate the efficiency and applicability of the developed techniques.
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| 10. |
- Holsmark, Rickard, 1970-
(författare)
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Deadlock Free Routing in Mesh Networks on Chip with Regions
- 2009
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- There is a seemingly endless miniaturization of electronic components, which has enabled designers to build sophisticated computing structureson silicon chips. Consequently, electronic systems are continuously improving with new and more advanced functionalities. Design complexity ofthese Systems on Chip (SoC) is reduced by the use of pre-designed cores. However, several problems related to the interconnection of coresremain. Network on Chip (NoC) is a new SoC design paradigm, which targets the interconnect problems using classical network concepts. Still,SoC cores show large variance in size and functionality, whereas several NoC benefits relate to regularity and homogeneity. This thesis studies some network aspects which are characteristic to NoC systems. One is the issue of area wastage in NoC due to cores of varioussizes. We elaborate on using oversized regions in regular mesh NoC and identify several new design possibilities. Adverse effects of regions oncommunication are outlined and evaluated by simulation. Deadlock freedom is an important region issue, since it affects both the usability and performance of routing algorithms. The concept of faultyblocks, used in deadlock free fault-tolerant routing algorithms has similarities with rectangular regions. We have improved and adopted one suchalgorithm to provide deadlock free routing in NoC with regions. This work also offers a methodology for designing topology agnostic, deadlockfree, highly adaptive application specific routing algorithms. The methodology exploits information about communication among tasks of anapplication. This is used in the analysis of deadlock freedom, such that fewer deadlock preventing routing restrictions are required. A comparative study of the two proposed routing algorithms shows that the application specific algorithm gives significantly higher performance.But, the fault-tolerant algorithm may be preferred for systems requiring support for general communication. Several extensions to our work areproposed, for example in areas such as core mapping and efficient routing algorithms. The region concept can be extended for supporting reuse ofa pre-designed NoC as a component in a larger hierarchical NoC.
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| 11. |
- Izosimov, Viacheslav, 1980-
(författare)
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Scheduling and Optimization of Fault-Tolerant Distributed Embedded Systems
- 2009
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Safety-critical applications have to function correctly and deliver high level of quality-ofservice even in the presence of faults. This thesis deals with techniques for tolerating effects of transient and intermittent faults. Re-execution, software replication, and rollback recovery with checkpointing are used to provide the required level of fault tolerance at the software level. Hardening is used to increase the reliability of hardware components. These techniques are considered in the context of distributed real-time systems with static and quasi-static scheduling.Many safety-critical applications have also strict time and cost constrains, which means that not only faults have to be tolerated but also the constraints should be satisfied. Hence, efficient system design approaches with careful consideration of fault tolerance are required. This thesis proposes several design optimization strategies and scheduling techniques that take fault tolerance into account. The design optimization tasks addressed include, among others, process mapping, fault tolerance policy assignment, checkpoint distribution, and trading-off between hardware hardening and software re-execution. Particular optimization approaches are also proposed to consider debugability requirements of fault-tolerant applications. Finally, quality-of-service aspects have been addressed in the thesis for fault-tolerant embedded systems with soft and hard timing constraints.The proposed scheduling and design optimization strategies have been thoroughly evaluated with extensive experiments. The experimental results show that considering fault tolerance during system-level design optimization is essential when designing cost-effective and high-quality fault-tolerant embedded systems.
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| 12. |
- Jiang, Ke
(författare)
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Security-Driven Design of Real-Time Embedded Systems
- 2015
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Real-time embedded systems (RTESs) have been widely used in modern society. And it is also very common to find them in safety and security critical applications, such as transportation and medical equipment. There are, usually, several constraints imposed on a RTES, for example, timing, resource, energy, and performance, which must be satisfied simultaneously. This makes the design of such systems a difficult problem.More recently, the security of RTESs emerges as a major design concern, as more and more attacks have been reported. However, RTES security, as a parameter to be considered during the design process, has been overlooked in the past. This thesis approaches the design of secure RTESs focusing on aspects that are particularly important in the context of RTES, such as communication confidentiality and side-channel attack resistance.Several techniques are presented in this thesis for designing secure RTESs, including hardware/software co-design techniques for communication confidentiality on distributed platforms, a global framework for secure multi-mode real-time systems, and a scheduling policy for thwarting differential power analysis attacks. All the proposed solutions have been extensively evaluated in a large amount of experiments, including two real-life case studies, which demonstrate the efficiency of the presented techniques.
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| 13. |
- Larsson, Anders, 1977-
(författare)
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Test Optimization for Core-based System-on-Chip
- 2008
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The semiconductor technology has enabled the fabrication of integrated circuits (ICs), which may include billions of transistors and can contain all necessary electronic circuitry for a complete system, so-called System-on-Chip (SOC). In order to handle design complexity and to meet short time-to-market requirements, it is increasingly common to make use of a modular design approach where an SOC is composed of pre-designed and pre-verified blocks of logic, called cores.Due to imperfections in the fabrication process, each IC must be individually tested. A major problem is that the cost of test is increasing and is becoming a dominating part of the overall manufacturing cost. The cost of test is strongly related to the increasing test-data volumes, which lead to longer test application times and larger tester memory requirement. For ICs designed in a modular fashion, the high test cost can be addressed by adequate test planning, which includes test-architecture design, test scheduling, test-data compression, and test sharing techniques.In this thesis, we analyze and explore several design and optimization problems related to core-based SOC test planning. We perform optimization of test sharing and test-data compression. We explore the impact of test compression techniques on test application time and compression ratio. We make use of analysis to explore the optimization of test sharing and test-data compression in conjunction with test-architecture design and test scheduling. Extensive experiments, based on benchmarks and industrial designs, have been performed to demonstrate the significance of our techniques.
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| 14. |
- Lifa, Adrian Alin
(författare)
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Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms
- 2015
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Modern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as exibility, energy-eciency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on recongurable and heterogeneous platforms. We focus on performance enhancement for dynamically recongurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have conrmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems.
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| 15. |
- Maghazeh, Arian, 1985-
(författare)
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System-Level Design of GPU-Based Embedded Systems
- 2018
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Modern embedded systems deploy several hardware accelerators, in a heterogeneous manner, to deliver high-performance computing. Among such devices, graphics processing units (GPUs) have earned a prominent position by virtue of their immense computing power. However, a system design that relies on sheer throughput of GPUs is often incapable of satisfying the strict power- and time-related constraints faced by the embedded systems.This thesis presents several system-level software techniques to optimize the design of GPU-based embedded systems under various graphics and non-graphics applications. As compared to the conventional application-level optimizations, the system-wide view of our proposed techniques brings about several advantages: First, it allows for fully incorporating the limitations and requirements of the various system parts in the design process. Second, it can unveil optimization opportunities through exposing the information flow between the processing components. Third, the techniques are generally applicable to a wide range of applications with similar characteristics. In addition, multiple system-level techniques can be combined together or with application-level techniques to further improve the performance.We begin by studying some of the unique attributes of GPU-based embedded systems and discussing several factors that distinguish the design of these systems from that of the conventional high-end GPU-based systems. We then proceed to develop two techniques that address an important challenge in the design of GPU-based embedded systems from different perspectives. The challenge arises from the fact that GPUs require a large amount of workload to be present at runtime in order to deliver a high throughput. However, for some embedded applications, collecting large batches of input data requires an unacceptable waiting time, prompting a trade-off between throughput and latency. We also develop an optimization technique for GPU-based applications to address the memory bottleneck issue by utilizing the GPU L2 cache to shorten data access time. Moreover, in the area of graphics applications, and in particular with a focus on mobile games, we propose a power management scheme to reduce the GPU power consumption by dynamically adjusting the display resolution, while considering the user's visual perception at various resolutions. We also discuss the collective impact of the proposed techniques in tackling the design challenges of emerging complex systems.The proposed techniques are assessed by real-life experimentations on GPU-based hardware platforms, which demonstrate the superior performance of our approaches as compared to the state-of-the-art techniques.
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| 16. |
- Mahfouzi, Rouhollah, 1989-
(författare)
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Security-Aware Design of Cyber-Physical Systems for Control Applications
- 2021
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- With cyber-physical systems opening to the outside world, security can no longer be considered a secondary issue. In this work, we focus on security threats to control applications in cyber-physical systems. We provide detection, prevention, and mitigation solutions to attacks considering the stringent resource constraints and important properties of such systems. First, we highlight some important properties of control applications that are used to design an intrusion detection and mitigation mechanism. We show how the control laws, derived from the physical properties of control applications, can facilitate the intrusion detection mechanism. We also use a resource management approach to maintain the performance of the control application under attack. Second, we elaborate on the challenges derived from sharing a processor among several controller tasks. We investigate the counter-intuitive timing anomalies that result from such resource sharing and introduce the Butterfly attack which exploits these anomalies. With the Butterfly attack, the adversary interferes with a low criticality and less protected task to change the timing behavior of the other tasks sharing the same platform. We experimentally show how this attack can indirectly destabilize a high criticality and, potentially, more protected task. Then, we consider real-time communication of control applications over a Time-Triggered Ethernet network. We demonstrate the impact of varying delays on control stability and identify the route and schedule constraints that are necessary to guarantee stability. On top of that, we study the impact of encryption and decryption delays on stability and employ a design space exploration approach to maximize security while continuing to satisfy stability guarantees.
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| 17. |
- Manolache, Sorin
(författare)
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Analysis and Optimisation of Real-Time Systems with Stochastic Behaviour
- 2005
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Embedded systems have become indispensable in our life: household appliances, cars, airplanes, power plant control systems, medical equipment, telecommunication systems, space technology, they all contain digital computing systems with dedicated functionality. Most of them, if not all, are real-time systems, i.e. their responses to stimuli have timeliness constraints.The timeliness requirement has to be met despite some unpredictable, stochastic behaviour of the system. In this thesis, we address two causes of such stochastic behaviour: the application and platform-dependent stochastic task execution times, and the platform-dependent occurrence of transient faults on network links in networks-on-chip.We present three approaches to the analysis of the deadline miss ratio of applications with stochastic task execution times. Each of the three approaches fits best to a different context. The first approach is an exact one and is efficiently applicable to monoprocessor systems. The second approach is an approximate one, which allows for designer-controlled trade-off between analysis accuracy and analysis speed. It is efficiently applicable to multiprocessor systems. The third approach is less accurate but sufficiently fast in order to be placed inside optimisation loops. Based on the last approach, we propose a heuristic for task mapping and priority assignment for deadline miss ratio minimisation.Our contribution is manifold in the area of buffer and time constrained communication along unreliable on-chip links. First, we introduce the concept of communication supports, an intelligent combination between spatially and temporally redundant communication. We provide a method for constructing a sufficiently varied pool of alternative communication supports for each message. Second, we propose a heuristic for exploring the space of communication support candidates such that the task response times are minimised. The resulting time slack can be exploited by means of voltage and/or frequency scaling for communication energy reduction. Third, we introduce an algorithm for the worst-case analysis of the buffer space demand of applications implemented on networks-on-chip. Last, we propose an algorithm for communication mapping and packet timingfor buffer space demand minimisation.All our contributions are supported by sets of experimental results obtained from both synthetic and real-world applications of industrial size.
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| 18. |
- Rafiliu, Sergiu, 1983-
(författare)
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Stability of Adaptive Distributed Real-TimeSystems with Dynamic Resource Management
- 2013
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Today's embedded distributed real-time systems, are exposed to large variations in resource usage due to complex software applications, sophisticated hardware platforms, and the impact of their run-time environment. As eciency becomes more important, the applications running on these systems are extended with on-line resource managers whose job is to adapt the system in the face of such variations. Distributed systems are often heterogeneous, meaning that the hardware platform consists of computing nodes with dierent performance, operating systems, and scheduling policies, linked through one or more networks using dierent protocols.In this thesis we explore whether resource managers used in such distributed embedded systems are stable, meaning that the system's resource usage is controlled under all possible run-time scenarios. Stability implies a bounded worst-case behavior of the system and can be linked with classic real-time systems' properties such as bounded response times for the software applications. In the case of distributed systems, the stability problem is particularly hard because software applications distributed over the dierent resources generate complex, cyclic dependencies between the resources, that need to be taken into account. In this thesis we develop a detailed mathematical model of an adaptive, distributed real-time system and we derive conditions that, if satised, guarantee its stability.
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| 19. |
- Samii, Soheil, 1981-
(författare)
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Quality-Driven Synthesis and Optimization of Embedded Control Systems
- 2011
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This thesis addresses several synthesis and optimization issues for embedded control systems. Examples of such systems are automotive and avionics systems in which physical processes are controlled by embedded computers through sensor and actuator interfaces. The execution of multiple control applications, spanning several computation and communication components, leads to a complex temporal behavior that affects control quality. The relationship between system timing and control quality is a key issue to consider across the control design and computer implementation phases in an integrated manner. We present such an integrated framework for scheduling, controller synthesis, and quality optimization for distributed embedded control systems.At runtime, an embedded control system may need to adapt to environmental changes that affect its workload and computational capacity. Examples of such changes, which inherently increase the design complexity, are mode changes, component failures, and resource usages of the running control applications. For these three cases, we present trade-offs among control quality, resource usage, and the time complexity of design and runtime algorithms for embedded control systems.The solutions proposed in this thesis have been validated by extensive experiments. The experimental results demonstrate the efficiency and importance of the presented techniques.
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| 20. |
- Tanasa, Bogdan, 1985-
(författare)
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Timing Analysis of Distributed Embedded Systems with Stochastic Workload and Realiability Constraints
- 2015
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Today's distributed embedded systems are exposed to large variations in workload due to complex software applications and sophisticated hardware platforms. Examples of such systems are automotive and avionics applications.The tasks running on computational units have variable execution times. Thus, the workload that the computational units must accommodate is likely to be stochastic. Some of the tasks trigger messages that will be transmitted over communication buses. There is a direct connection between the variable execution times of the tasks and the moments of triggering of these messages. Thus, the workload imposed on the communication buses will also be stochastic. The likelihood for transient faults to occur is another dimension for stochastic workload as today's embedded systems are designed to work in extreme environmental conditions. Given the above, the need for tools that can analyze systems that experience stochastic workload is continuously increasing.The present thesis addresses this need. The solutions proposed in this thesis have been validated by extensive experiments that demonstrate the efficiency of the presented techniques.
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| 21. |
- Ukhov, Ivan, 1986-
(författare)
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System-Level Analysis and Design under Uncertainty
- 2017
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- One major problem for the designer of electronic systems is the presence of uncertainty, which is due to phenomena such as process and workload variation. Very often, uncertainty is inherent and inevitable. If ignored, it can lead to degradation of the quality of service in the best case and to severe faults or burnt silicon in the worst case. Thus, it is crucial to analyze uncertainty and to mitigate its damaging consequences by designing electronic systems in such a way that uncertainty is effectively and efficiently taken into account.We begin by considering techniques for deterministic system-level analysis and design of certain aspects of electronic systems. These techniques do not take uncertainty into account, but they serve as a solid foundation for those that do. Our attention revolves primarily around power and temperature, as they are of central importance for attaining robustness and energy efficiency. We develop a novel approach to dynamic steady-state temperature analysis of electronic systems and apply it in the context of reliability optimization.We then proceed to develop techniques that address uncertainty. The first technique is designed to quantify the variability in process parameters, which is induced by process variation, across silicon wafers based on indirect and potentially incomplete and noisy measurements. The second technique is designed to study diverse system-level characteristics with respect to the variability originating from process variation. In particular, it allows for analyzing transient temperature profiles as well as dynamic steady-state temperature profiles of electronic systems. This is illustrated by considering a problem of design-space exploration with probabilistic constraints related to reliability. The third technique that we develop is designed to efficiently tackle the case of sources of uncertainty that are less regular than process variation, such as workload variation. This technique is exemplified by analyzing the effect that workload units with uncertain processing times have on the timing-, power-, and temperature-related characteristics of the system under consideration.We also address the issue of runtime management of electronic systems that are subject to uncertainty. In this context, we perform an early investigation into the utility of advanced prediction techniques for the purpose of fine-grained long-range forecasting of resource usage in large computer systems.All the proposed techniques are assessed by extensive experimental evaluations, which demonstrate the superior performance of our approaches to analysis and design of electronic systems compared to existing techniques.
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| 22. |
- Cortés, Luis Alejandro, 1971-
(författare)
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A Petri Net based Modeling and Verification Technique for Real-Time Embedded Systems
- 2001
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Embedded systems are used in a wide spectrum of applications ranging from home appliances and mobile devices to medical equipment and vehicle controllers. They are typically characterized by their real-time behavior and many of them must fulfill strict requirements on reliability and correctness.In this thesis, we concentrate on aspects related to modeling and formal verification of realtime embedded systems.First, we define a formal model of computation for real-time embedded systems based on Petri nets. Our model can capture important features of such systems and allows their representations at different levels of granularity. Our modeling formalism has a welldefined semantics so that it supports a precise representation of the system, the use of formal methods to verify its correctness, and the automation of different tasks along the design process.Second, we propose an approach to the problem of formal verification of real-time embedded systems represented in our modeling formalism. We make use of model checking to prove whether certain properties, expressed as temporal logic formulas, hold with respect to the system model. We introduce a systematic procedure to translate our model into timed automata so that it is possible to use available model checking ools. Various examples, including a realistic industrial case, demonstrate the feasibility of our approach on practical applications.
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| 23. |
- He, Zhiyuan, 1976-
(författare)
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System-on-Chip test scheduling with defect-probability and temperature considerations
- 2007
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Electronic systems have become highly complex, which results in a dramatic increase of both design and production cost. Recently a core-based system-on-chip (SoC) design methodology has been employed in order to reduce these costs. However, testing of SoCs has been facing challenges such as long test application time and high temperature during test. In this thesis, we address the problem of minimizing test application time for SoCs and propose three techniques to generate efficient test schedules.First, a defect-probability driven test scheduling technique is presented for production test, in which an abort-on-first-fail (AOFF) test approach is employed and a hybrid built-in self-test architecture is assumed. Using an AOFF test approach, the test process can be aborted as soon as the first fault is detected. Given the defect probabilities of individual cores, a method is proposed to calculate the expected test application time (ETAT). A heuristic is then proposed to generate test schedules with minimized ETATs.Second, a power-constrained test scheduling approach using test set partitioning is proposed. It assumes that, during the test, the total amount of power consumed by the cores being tested in parallel has to be lower than a given limit. A heuristic is proposed to minimize the test application time, in which a test set partitioning technique is employed to generate more efficient test schedules.Third, a thermal-aware test scheduling approach is presented, in which test set partitioning and interleaving are employed. A constraint logic programming (CLP) approach is deployed to find the optimal solution. Moreover, a heuristic is also developed to generate near-optimal test schedules especially for large designs to which the CLP-based algorithm is inapplicable.Experiments based on benchmark designs have been carried out to demonstrate the applicability and efficiency of the proposed techniques.
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| 24. |
- Karlsson, Daniel, 1975-
(författare)
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Verification of Component-based Embedded System Designs
- 2006
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex. Designers handle this increasing complexity by reusing existing components. At the same time, the systems must fulfill strict functional and non-functional requirements.This thesis presents novel and efficient techniques for the verification of component-based embedded system designs. As a common basis, these techniques have been developed using a Petri net based modelling approach, called PRES+.Two complementary problems are addressed: component verification and integration verification. With component verification the providers verify their components so that they function correctly if given inputs conforming to the assumptions imposed by the components on their environment.Two techniques for component verification are proposed in the thesis. The first technique enables formal verification of SystemC designs by translating them into the PRES+ representation. The second technique involves a simulation based approach into which formal methods are injected to boost verification efficiency.Provided that each individual component is verified and is guaranteed to function correctly, the components are interconnected to form a complete system. What remains to be verified is the interface logic, also called glue logic, and the interaction between components.Each glue logic and interface cannot be verified in isolation. It must be put into the context in which it is supposed to work. An appropriate environment must thus be derived from the components to which the glue logic is connected. This environment must capture the essential properties of the whole system with respect to the properties being verified. In this way, both the glue logic and the interaction of components through the glue logic are verified. The thesis presents algorithms for automatically creating such environments as well as the underlying theoretical framework and a step-by-step roadmap on how to apply these algorithms.
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| 25. |
- Larsson, Anders, 1977-
(författare)
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System-on-Chip Test Scheduling and Test Infrastructure Design
- 2005
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- There are several challenges that have to be considered in order to reduce the cost of System-on-Chip (SoC) testing, such as test application time, chip area overhead due to hardware introduced to enhance the testing, and the price of the test equipment. In this thesis the test application time and the test infrastructure hardware overhead of multiple-core SoCs are considered and two different problems are addressed. First, a technique that makes use of the existing bus structure on the chip for transporting test data is proposed. Additional buffers are inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. A test controller is introduced, which is responsible for the invocation of test transportations on the bus. The hardware cost, introduced by the buffers and test controller, is minimized under a designer-specified test time constraint. This problem has been solved optimally by using a Constraint Logic Programming formulation, and a tabu search based heuristic has also been implemented to generate quickly near-optimal solutions. Second, a technique to broadcast tests to several cores is proposed, and the possibility to use overlapping test vectors from different tests in a SoC is explored. The overlapping tests serve as alternatives to the original, dedicated, tests for the individual cores and, if selected, they are broadcasted to the cores so that several cores are tested concurrently. This technique allows the existing bus structure to be reused; however, dedicated test buses can also be introduced in order to reduce the test time. Our objective is to minimize the test application time while a designer-specified hardware constraint is satisfied. Again Constraint Logic Programming has been used to solve the problem optimally. Experiments using benchmark designs have been carried out to demonstrate the usefulness and efficiency of the proposed techniques.
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| 26. |
- Mohamed, Abdil, 1971-
(författare)
-
High-Level Techniques for Built-In Self-Test Resources Optimization
- 2005
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Design modifications to improve testability usually introduce large area overhead and performance degradation. One way to reduce the negative impact associated with improved testability is to take testability as one of the constraints during high- level design phases so that systems are not only optimized for area and performance, but also from the testability point of view. This thesis deals with the problem of optimizing testing-hardware resources by taking into account testability constraints at high-levels of abstraction during the design process. Firstly, we have provided an approach to solve the problem of optimizing built-in selftest (BIST) resources at the behavioral and register-transfer levels under testability and testing time constraints. Testing problem identification and BIST enhancement during the optimization process are assisted by symbolic testability analysis. Further, concurrent test sessions are generated, while signature analysis registers sharing conflicts as well as controllability and observability constraints are considered. Secondly, we have introduced the problem of BIST resources insertion and optimization while taking wiring area into account. Testability improvement transformations have been defined and deployed in a hardware overhead minimization technique used during a BIST synthesis process. The technique is guided by the results of symbolic testability analysis and inserts a minimal amount of BIST resources into the design to make it fully testable. It takes into consideration both BIST components cost and wiring overhead. Two design space exploration approaches have been proposed: a simulated annealing based algorithm and a greedy heuristic. Experimental results show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. The greedy heuristic uses our behavioral and register-transfer levels BIST enhancement metrics to guide BIST synthesis in such a way that the number of testability improvement transformations performed on the design is reduced.
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| 27. |
- Mubeen, Saad
(författare)
-
Communications-Oriented Modeling and Development of Vehicular Distributed Embedded Systems
- 2014
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The model- and component-based development approach has emerged as an attractive option for the development of vehicular distributed real-time embedded systems. Within this context we target challenges related to modeling of legacy network communication, extraction of end-to-end timing models and support for end-to-end timing analysis.We propose a novel approach for modeling legacy network communication in these systems. By introducing special-purpose components to encapsulate and abstract the communication protocols, we allow the use of legacy nodes and legacy protocols in a component- and model-based software engineering environment. Because an end-to-end timing model should be available to perform the end-to-end response-time and delay analyses, we present a method to extract the timing models from these systems. We also extend the method to various abstraction levels and parts of the development process for the systems. During the models extraction, we identify that the existing worst-case response-time analysis for Controller Area Network (CAN), a widely used real-time network protocol in the vehicular domain, does not support mixed messages. These messages are partly periodic and partly sporadic. They are implemented by some higher-level protocols for CAN used in the industry. We extend the existing analysis which is now applicable to any higher-level protocol for CAN that uses periodic, sporadic and/or mixed transmission.In order to show the application of our modeling techniques, timing model extraction method and extended analyses; we provide a proof of concept by extending the Rubus Component Model, which is used for the development of software for vehicular embedded real-time systems by several international companies. We also implement the end-to-end response-time and delay analyses along with the extended analysis for CAN in the existing industrial tool suite the Rubus-ICE. Moreover, we implement the extended analysis for CAN in a free tool MPS-CAN analyzer. Further, we conduct automotive-application case studies to validate our methods and techniques.
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| 28. |
- Pop, Paul, 1974-
(författare)
-
Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems
- 2003
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Embedded computer systemsare now everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded computer systems. An important class of embedded computer systems is that of real-time systems, which have to fulfill strict timing requirements. As real-time systems become more complex, they are often implemented using distributed heterogeneous architectures. The main objective of the thesis is to develop analysis and synthesis methods for communication-intensive heterogeneous hard real-time systems. The systems are heterogeneous not only in terms of platforms and communication protocols, but also in terms of scheduling policies. Regarding this last aspect, in this thesis we consider time-driven systems, event-driven systems, and a combination of both, called multi-cluster systems. The analysis takes into account the heterogeneous interconnected nature of the architecture, and is based on an application model that captures both the dataflow and the flow of control. The proposed synthesis techniques derive optimized implementations of the system that fulfill the design constraints. An important part of the system implementation is the synthesis of the communication infrastructure, which has a significant impact on the overall system performance and cost. To reduce the time-to-market of products, the design of real-time systems seldom starts from scratch. Typically, designers start from an already existing system, running certain applications, and the design problem is to implement new functionality on top of this system. Hence, in addition to the analysis and synthesis methods proposed, we have also considered mapping and scheduling within such an incremental design process. The analysis and synthesis techniques proposed have been thoroughly evaluated using a solid experimental platform. Besides the evaluations, performed using a large number of generated example applications, we have also validated our approaches using a realistic case study consisting of a vehicle cruise controller.
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| 29. |
- Pop, Paul, 1974-
(författare)
-
Scheduling and Communication Synthesis for Distributed Real-Time Systems
- 2000
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Embedded systems are now omnipresent: from cellular phones to pagers, from microwave ovens to PDAs, almost all the devices we use are controlled by embedded systems. Many embedded systems have to fulfill strict requirements in terms of performance and cost efficiency. Emerging designs are usually based on heterogeneous architectures that integrate multiple programmable processors and dedicated hardware components. New tools which extend design automation to system level have to support the integrated design of both the hardware and software components of such systems. This thesis concentrates on aspects of scheduling and communication for embedded real-time systems. Special emphasis has been placed on the impact of the communication infrastructure and protocol on the overall system performance. The scheduling and communication strategies proposed are based on an abstract graph representation which captures, at process level, both the dataflow and the flow of control. We have considered non-preemptive static cyclic scheduling and preemptive scheduling with static priorities for the scheduling of processes, while the communications are statically scheduled according to the time triggered protocol. We have developed static cyclic scheduling algorithms for time-driven systems with control and data dependencies. We show that by considering aspects of the communication protocol, significant improvements can be gained in the schedule quality. In the context of event-driven systems we have proposed a less pessimistic schedulability analysis that is able to handle both control and data dependencies. Moreover, we have provided a schedulability analysis for the time-triggered protocol, and we have proposed several optimization strategies for the synthesis of communication protocol parameters. Extensive experiments as well as real-life examples demonstrate the efficiency of our approaches.
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| 30. |
- Pop, Ruxandra
(författare)
-
Mapping Concurrent Applications to Multiprocessor Systems with Multithreaded Processors and Network on Chip-Based Interconnections
- 2011
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Network on Chip (NoC) architectures provide scalable platforms for designing Systems on Chip (SoC) with large number of cores. Developing products and applications using an NoC architecture offers many challenges and opportunities. A tool which can map an application or a set of applications to a given NoC architecture will be essential.In this thesis we first survey current techniques and we present our proposals for mapping and scheduling of concurrent applications to NoCs with multithreaded processors as computational resources.NoC platforms are basically a special class of Multiprocessor Embedded Systems (MPES). Conventional MPES architectures are mostly bus-based and, thus, are exposed to potential difficulties regarding scalability and reusability. There has been a lot of research on MPES development including work on mapping and scheduling of applications. Many of these results can also be applied to NoC platforms.Mapping and scheduling are known to be computationally hard problems. A large range of exact and approximate optimization algorithms have been proposed for solving these problems. The methods include Branch-and–Bound (BB), constructive and transformative heuristics such as List Scheduling (LS), Genetic Algorithms (GA) and various types of Mathematical Programming algorithms.Concurrent applications are able to capture a typical embedded system which is multifunctional. Concurrent applications can be executed on an NoC which provides a large computational power with multiple on-chip computational resources.Improving the time performances of concurrent applications which are running on Network on Chip (NoC) architectures is mainly correlated with the ability of mapping and scheduling methodologies to exploit the Thread Level Parallelism (TLP) of concurrent applications through the available NoC parallelism. Matching the architectural parallelism to the application concurrency for obtaining good performance-cost tradeoffs is another aspect of the problem.Multithreading is a technique for hiding long latencies of memory accesses, through the overlapped execution of several threads. Recently, Multi-Threaded Processors (MTPs) have been designed providing the architectural infrastructure to concurrently execute multiple threads at hardware level which, usually, results in a very low context switching overhead. Simultaneous Multi-Threaded Processors (SMTPs) are superscalar processor architectures which adaptively exploit the coarse grain and the fine grain parallelism of applications, by simultaneously executing instructions from several thread contexts.In this thesis we make a case for using SMTPs and MTPs as NoC resources and show that such a multiprocessor architecture provides better time performances than an NoC with solely General-purpose Processors (GP). We have developed a methodology for task mapping and scheduling to an NoC with mixed SMTP, MTP and GP resources, which aims to maximize the time performance of concurrent applications and to satisfy their soft deadlines. The developed methodology was evaluated on many configurations of NoC-based platforms with SMTP, MTP and GP resources. The experimental results demonstrate that the use of SMTPs and MTPs in NoC platforms can significantly speed-up applications.
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| 31. |
- Rosén, Jakob, 1977-
(författare)
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Predictable Real-Time Applications on Multiprocessor Systems-on-Chip
- 2011
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Being predictable with respect to time is, by definition, a fundamental requirement for any real-time system. Modern multiprocessor systems impose a challenge in this context, due to resource sharing conflicts causing memory transfers to become unpredictable. In this thesis, we present a framework for achieving predictability for real-time applications running on multiprocessor system-on-chip platforms. Using a TDMA bus, worst-case execution time analysis and scheduling are done simultaneously. Since the worst-case execution times are directly dependent on the bus schedule, bus access design is of special importance. Therefore, we provide an efficient algorithm for generating bus schedules, resulting in a minimized worst-case global delay.We also present a new approach considering the average-case execution time in a predictable context. Optimization techniques for improving the average-case execution time of tasks, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this thesis, we show that having a good average-case global delay can be important also for real-time applications, for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing for the average case and the worst case simultaneously, allowing for a good average case execution time while still keeping the worst case as small as possible. The proposed solutions in this thesis have been validated by extensive experiments. The results demonstrate the efficiency and importance of the presented techniques.
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| 32. |
- Andrei, Alexandru, 1977-
(författare)
-
Energy Efficient and Predictable Design of Real-Time Embedded Systems
- 2007
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This thesis addresses several issues related to the design and optimization of embedded systems. In particular, in the context of time-constrained embedded systems, the thesis investigates two problems: the minimization of the energy consumption and the implementation of predictable applications on multiprocessor system-on-chip platforms.Power consumption is one of the most limiting factors in electronic systems today. Two techniques that have been shown to reduce the power consumption effectively are dynamic voltage selection and adaptive body biasing. The reduction is achieved by dynamically adjusting the voltage and performance settings according to the application needs. Energy minimization is addressed using both offline and online optimization approaches. Offline, we solve optimally the combined supply voltage and body bias selection problem for multiprocessor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. The voltage selection technique is applied not only to processors, but also to buses with repeaters and fat wires. We investigate the continuous voltage selection as well as its discrete counterpart. While the above mentioned methods minimize the active energy, we propose an approach that combines voltage selection and processor shutdown in order to optimize the total energy.In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the voltage and performance settings during run-time, i.e., online. However, voltage scaling is computationally expensive, and, thus, performed at runtime, significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static voltage scaling scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the voltage settings.Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system’s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks’ WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.
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| 33. |
- Izosimov, Viacheslav, 1980-
(författare)
-
Scheduling and Optimization of Fault-Tolerant Embedded Systems
- 2006
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Safety-critical applications have to function correctly even in presence of faults. This thesis deals with techniques for tolerating effects of transient and intermittent faults. Reexecution, software replication, and rollback recovery with checkpointing are used to provide the required level of fault tolerance. These techniques are considered in the context of distributed real-time systems with non-preemptive static cyclic scheduling.Safety-critical applications have strict time and cost constrains, which means that not only faults have to be tolerated but also the constraints should be satisfied. Hence, efficient system design approaches with consideration of fault tolerance are required.The thesis proposes several design optimization strategies and scheduling techniques that take fault tolerance into account. The design optimization tasks addressed include, among others, process mapping, fault tolerance policy assignment, and checkpoint distribution.Dedicated scheduling techniques and mapping optimization strategies are also proposed to handle customized transparency requirements associated with processes and messages. By providing fault containment, transparency can, potentially, improve testability and debugability of fault-tolerant applications.The efficiency of the proposed scheduling techniques and design optimization strategies is evaluated with extensive experiments conducted on a number of synthetic applications and a real-life example. The experimental results show that considering fault tolerance during system-level design optimization is essential when designing cost-effective fault-tolerant embedded systems.
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| 34. |
- Liu, Meng
(författare)
-
On Improving Resource Utilization in Distributed Real-Time Embedded Systems
- 2014
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In our modern life, embedded systems are playing an essential role. An embedded system is a computer system embedded into a certain device, in order to achieve computing functions. Beyond all doubt, as a validated system, the functional correctness must be guaranteed. However, for many embedded systems, timeliness also plays an important role in addition to the correctness of the functionalities. For example, in an automotive braking system, the braking function needs to be processed within a limited time duration in order to avoid accidents. Such systems are known as real-time embedded systems.In these systems, there can be plenty of software programs (called tasks) sharing limited computing resources (e.g. processors, memories). If the system executes tasks in a random way, the whole system will become unpredictable. As a result, the system designers will not be able to verify if the system design can fulfill all the timing requirements or not. In other words, the system is not guaranteed to be safe. Therefore, system designers need to carefully implement algorithms to schedule all the tasks in a predictable manner. Regarding each scheduling algorithm, schedulability analyses are proposed which are used to check if the requirements can be satisfied.Unfortunately, many real-time systems reserve too much computing resource for the sake of fulfilling timing requirements, without taking into account resource utilization. As a result, system resources cannot be efficiently utilized, which can cause significant resource waste in reality. Therefore, in this thesis, we aim to improve resource utilization in modern distributed real-time embedded systems. We try to tackle this problem from the following two aspects.Investigating tighter timing analyses. Due to the difficulty in performing precise mathematical schedulability analyses, most of the existing analyses include varying degrees of pessimism. In other words, the actual performance of the system can be much better than the predictions. If we can reduce the pessimism in schedulability analyses, we can then admit more workload into the system.Proposing new scheduling frameworks. It is difficult to find a scheduling algorithm which is suitable for all the situations. Therefore, we need different mechanisms to handle specific system characteristics in order to improve the resource utilization.
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| 35. |
- Pop, Traian, 1975-
(författare)
-
Analysis and Optimisation of Distributed Embedded Systems with Heterogeneous Scheduling Policies
- 2007
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The growing amount and diversity of functions to be implemented by the current and future embedded applications (like, for example, in automotive electronics) have shown that, in many cases, time-triggered and event-triggered functions have to coexist on the computing nodes and to interact over the communication infrastructure. When time-triggered and event-triggered activities have to share the same processing node, a natural way for the execution support can be provided through a hierarchical scheduler. Similarly, when such heterogeneous applications are mapped over a distributed architecture, the communication infrastructure should allow for message exchange in both time-triggered and event-triggered manner in order to ensure a straightforward interconnection of heterogeneous components.This thesis studies aspects related to the analysis and design optimisation for safety-critical hard real-time applications running on hierarchically scheduled distributed embedded systems. It first provides the basis for the timing analysis of the activities in such a system, by carefully taking into consideration all the interferences that appear at run-time between the processes executed according to different scheduling policies. Moreover, due to the distributed nature of the architecture, message delays are also taken into consideration during the timing analysis. Once the schedulability analysis has been provided, the entire system can be optimised by adjusting its configuration parameters. In our work, the entire optimisation process is directed by the results from the timing analysis, with the goal that in the end the timing constraints of the application are satisfied. The analysis and design methodology proposed in the first part of the thesis is applied next on the particular category of distributed systems that use FlexRay as a communication protocol. We start by providing a schedulability analysis for messages transmitted over a FlexRay bus, and then by proposing a bus access optimisation algorithm that aims at improving the timing properties of the entire system.For all the problems that we investigated, we have carried out extensive experiments in order to measure the efficiency of the proposed solutions. The results have confirmed both the importance of the addressed aspects during system-level design, and the applicability of our techniques for analysing and optimising the studied systems.
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| 36. |
- Pozo Pérez, Francisco Manuel
(författare)
-
Methods for Efficient and Adaptive Scheduling of Next-Generation Time-Triggered Networks
- 2019
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Real-time networks play a fundamental role in embedded systems. To meet timing requirements, provide low jitter and bounded latency in such networks the time-triggered communication paradigm is frequently applied in such networks. In this paradigm, a schedule specifying the transmission times of all the traffic is synthesized a priori. Given the steady increase in size and complexity of embedded systems, coupled with the addition of wireless communication, a new time-triggered network model of larger and mixed wired-wireless network isdeveloping. Developing such next-generation networks entails significant research challenges, especially concerning scalability, i.e., allowing generation of schedules of the very large next-generation networks in a reasonable time. A second challenge concerns a well-known limitation of the time-triggered paradigm: its lack of flexibility. Large networks exacerbate this problem, as the number of changes during network operation increases with the number of components, which renders static scheduling approaches unsuitable.In this thesis, we first propose a remedy to the scalability challenge that the synthesis of next-generation network schedules introduces. We propose a family of divide-and-conquer approaches that segment the entire scheduling problem into small enough subproblems that can be effectively and efficiently solved by state-of-the-art schedulers. Second, we investigate how adaptive behaviours can be introduced into the time-triggered paradigm with the implementation of a Self-Healing Protocol. This protocol addresses the flexibility challenge by only updating a small segment of the schedule in response to changes during runtime. This provides a significant advantage compared to current approaches that fully reschedule the network. In the course of our research, we found that our protocol become more effective when the slack in the original schedule is evenly distributed during the schedule synthesis. As a consequence, we also propose a new scheduling approach that maximizes the distances between frames, increasing the success rate of our protocol.The divide-and-conquer approaches developed in this thesis were able to synthesize schedules of two orders of magnitude more traffic and one order of magnitude more nodes in less than four hours. Moreover, when applied to current industrial size networks, they reduced the synthesis time from half an hour to less than one minute compared with state-of-the-art schedulers. The Self-Healing Protocol opened a path towards adaptive time-triggered being able to heal schedules online after link and switch failures in less than ten milliseconds.
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