| 1. |
|
|
| 2. |
- Dubrova, Elena, et al.
(författare)
-
TOP : an algorithm for three-level combinational logic optimisation
- 2004
-
Ingår i: IEE Proceedings - Circuits Devices and Systems. - : Institution of Engineering and Technology (IET). - 1350-2409 .- 1359-7000. ; 151:4, s. 307-314
-
Tidskriftsartikel (refereegranskat)abstract
- Three-level logic is shown to have a potential for reducing the area over two-level implementations, as well as for a gain in speed over multilevel implementations. A heuristic algorithm TOP is presented, targeting a three-level logic expression of type g(1degrees)g(2), where g(1) and g(2) are sum-of-products expressions and '(degrees)' is a binary operation. For the first time, to the authors' knowledge, this problem is addressed for an arbitrary operation '(degrees)', although several algorithms for specified cases of '(degrees)' have been presented in the past. The experimental results show that, on average, the total number of product-terms in the expression obtained by TOP is about one third of the number of product-terms in the expression obtained by a two-level AND-OR minimiser.
|
|
| 3. |
|
|
| 4. |
- Jantsch, A, et al.
(författare)
-
Comparison of Six Languages for System Level Descriptions of Telecom Systems
- 2001
-
Ingår i: Electronic Chips & Systems Design Languages. - Boston, Mass. : Kluwer Academic Publishers. - 0792373111 ; , s. 320-
-
Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- Language evaluation for various purposes is an often repeated exercise in industry and academia. Due to the large number of influencing factors the dependence of the result on implicit or explicit assumptions is not always apparent and clear. Based on a systematic evaluation method with a large number of criteria we compare six languages with respect to the suitability as a system specification and description language for telecom applications. The languages under evaluation are VHDL, C++, SDL, Haskell, Erlang, and ProGram, which represent different paradigms. The evaluation method allows to give specific emphasis on particular aspects in a controlled way, which we use to make separate comparisons for pure software systems, pure hardware systems and mixed HW/SW systems.
|
|
| 5. |
- Jantsch, A, et al.
(författare)
-
Conparison of six languages for system level descriptions of telecom systems
- 1998
-
Ingår i: Proceedings / FDL'98 / First International Forum on Design Languages. - Lausanne : Swiss Federal Inst. Of techn.. ; , s. 160-
-
Konferensbidrag (refereegranskat)abstract
- Language evaluation for various purposes is an often repeated exercise in industry and academia. Due to the large number of influencing factors the dependence of the result on implicit or explicit assumptions is not always apparent and clear. Based on a systematic evaluation method with a large number of criteria we compare six languages with respect to the suitability as a system specification and description language for telecom applications. The languages under evaluation are VHDL, C++, SDL, Haskell, Erlang, and ProGram, which represent different paradigms. The evaluation method allows to give specific emphasis on particular aspects in a controlled way, which we use to make separate comparisons for pure software systems, pure hardware systems and mixed HW/SW systems.
|
|
| 6. |
- Tajammul, Muhammad Adeel, et al.
(författare)
-
TransMem : A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs
- 2017
-
Ingår i: Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509007332 ; , s. 92-99
-
Konferensbidrag (refereegranskat)abstract
- In the nano scale era, the upcoming design challenges like dark silicon, power wall, and memory wall have prompted extensive research into the architectural alternatives to the general purpose processor. Coarse Grained Reconfig-urable Architectures (CGRAs) are emerging as one of the promising alternatives. Commonly, CGRAs are composed of a computation layer and a memory layer. Tempted by higher platform utilization and energy efficiency, recently proposed CGRAs offer dynamic remapping and parallelism. However, the existing works only address the computational elements, while for many applications the bulk of energy is consumed by the memory and memory accesses. Therefore, without architectural support to optimize the memory contents, according to the changes in computational layer, the benefits promised by dynamic parallelism and remapping are severely degraded. As a solution to this problem we present TransMem, a supporting memory infrastructure that complements the dynamic remapping and parallelism in the computational fabric. Simulation results reveal that the additional flexibility enhances the energy efficiency by up to 85% for the tested applications, compared to state of the art. Post-layout analysis reveals that TransMem incurs only 4% area penalty.
|
|
| 7. |
|
|
