| 1. |
- Ahmed, Tanvir, et al.
(författare)
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A 512-point 8-parallel pipelined feedforward FFT for WPAN
- 2011
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Ingår i: 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR). - : IEEE. ; , s. 981-984
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Konferensbidrag (refereegranskat)abstract
- This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides, the proposed architecture uses the minimum memory that is required for a 512-point 8-parallel FFT. Experimental results show that besides its high throughput, the design is efficient in area and power consumption, improving the results of previous approaches. Specifically, for a wordlength of 16 bits, the proposed design consumes 61.5 mW and its area is 1.43 mm2.
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| 2. |
- Ambuluri, Sreehari, et al.
(författare)
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New Radix-2 and Radix-22 Constant Geometry Fast Fourier Transform Algorithms For GPUs
- 2013
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Konferensbidrag (refereegranskat)abstract
- This paper presents new radix-2 and radix-22 constant geometry fast Fourier transform (FFT) algorithms for graphics processing units (GPUs). The algorithms combine the use of constant geometry with special scheduling of operations and distribution among the cores. Performance tests on current GPUs show a significant improvements compared to the most recent version of NVIDIA’s well-known CUFFT, achieving speedups of up to 5.6x.
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| 3. |
- Garrido, Mario, 1981-, et al.
(författare)
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A Pipelined FFT Architecture for Real-Valued Signals
- 2009
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 56:12, s. 2634-2643
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fast Fourier trans-form (RFFT). The proposed architecture takes advantage of the re-duced number of operations of the RFFT with respect to the com-plex fast Fourier transform (CFFT), and requires less area whileachieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computa-tion of the RFFT, which, contrary to previous approaches, presentsa regular geometry suitable for the implementation of hardwarestructures. Moreover, the algorithm can be used for both the deci-mation in time (DIT) and decimation in frequency (DIF) decompo-sitions of the RFFT and requires the lowest number of operationsreported for radix 2.Finally, as in previous works, when calculating the RFFT theoutput samples are obtained in a scrambled order. The problemof reordering these samples is solved in this paper and a pipelinedcircuit that performs this reordering is proposed.
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| 4. |
- Garrido, Mario, 1981-, et al.
(författare)
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Challenging the Limits of FFT Performance on FPGAs
- 2014
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Konferensbidrag (refereegranskat)abstract
- This paper analyzes the limits of FFT performance on FPGAs. For this purpose, a FFT generation tool has been developed. This tool is highly parameterizable and allows for generating FFTs with different FFT sizes and amount of parallelization. Experimental results for FFT sizes from 16 to 65536, and 4 to 64 parallel samples have been obtained. They show that even the largest FFT architectures fit well in today's FPGAs, achieving throughput rates from several GSamples/s to tens of GSamples/s.
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| 5. |
- Garrido, Mario, 1981-, et al.
(författare)
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Efficient Memoryless Cordic for FFT Computation
- 2007
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Ingår i: Efficient Memoryless Cordic for FFT Computation. - : IEEE. - 1424407281 - 1424407273 ; , s. II-113-II-116
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Konferensbidrag (refereegranskat)abstract
- A new memoryless CORDIC algorithm for the FFT computation is proposed in this paper. This approach calculates the direction of the micro-rotations from the control counter of the FFT, so the area of the rotator hardly depends on the number of rotations, which is particularly suitable for the computation of FFTs of a high number of points. Moreover, the new CORDIC presents other advantages such as the simplification of the basic CORDIC processor used to calculate the micro-rotations, or an easy way to compensate the intrinsic gain of the CORDIC algorithm. Additionally, the VLSI implementation of the algorithm is a pipeline architecture with high performance in terms of speed, throughput and latency.
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| 6. |
- Garrido, Mario, 1981-
(författare)
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Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 66:4, s. 657-661
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents novel circuits for calculating the bit reversal on parallel data. The circuits consist of delays/memories and multiplexers, and have the advantage that they requires the minimum number of multiplexers among circuits for parallel bit reversal so far, as well as a small total memory.
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| 7. |
- Garrido, Mario, 1981-, et al.
(författare)
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Optimum Circuits for Bit-Dimension Permutations
- 2019
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 27:5, s. 1148-1160
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing any bit-dimension permutation into elementary bit-exchanges. Such decomposition is proven to achieve the theoretical minimum number of delays required for the permutation. This offers optimum solutions for multiple well-known problems in the literature that make use of bit-dimension permutations. This includes the design of permutation circuits for the fast Fourier transform, bit reversal, matrix transposition, stride permutations, and Viterbi decoders.
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| 8. |
- Garrido, Mario, 1981-, et al.
(författare)
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World’s Fastest FFT Architectures : Breaking the Barrier of 100 GS/s
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 66:4, s. 1507-1516
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The architectures are based on a fully parallel implementation of the FFT algorithm. In order to obtain the highest throughput while keeping the resource utilization low, we base our design on making use of advanced shift-and-add techniques to implement the rotators and on selecting the most suitable FFT algorithms for these architectures. Apart from high throughput and resource efficiency, we also guarantee high accuracy in the proposed architectures. For the implementation, we have developed an automatic tool that generates the architectures as a function of the FFT size, input word length and accuracy of the rotations. We provide experimental results covering various FFT sizes, FFT algorithms, and field-programmable gate array boards. These results show that it is possible to break the barrier of 100 GS/s for FFT calculation.
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| 9. |
- Kattge, Jens, et al.
(författare)
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TRY plant trait database - enhanced coverage and open access
- 2020
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Ingår i: Global Change Biology. - : Wiley-Blackwell. - 1354-1013 .- 1365-2486. ; 26:1, s. 119-188
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Tidskriftsartikel (refereegranskat)abstract
- Plant traits-the morphological, anatomical, physiological, biochemical and phenological characteristics of plants-determine how plants respond to environmental factors, affect other trophic levels, and influence ecosystem properties and their benefits and detriments to people. Plant trait data thus represent the basis for a vast area of research spanning from evolutionary biology, community and functional ecology, to biodiversity conservation, ecosystem and landscape management, restoration, biogeography and earth system modelling. Since its foundation in 2007, the TRY database of plant traits has grown continuously. It now provides unprecedented data coverage under an open access data policy and is the main plant trait database used by the research community worldwide. Increasingly, the TRY database also supports new frontiers of trait-based plant research, including the identification of data gaps and the subsequent mobilization or measurement of new data. To support this development, in this article we evaluate the extent of the trait data compiled in TRY and analyse emerging patterns of data coverage and representativeness. Best species coverage is achieved for categorical traits-almost complete coverage for 'plant growth form'. However, most traits relevant for ecology and vegetation modelling are characterized by continuous intraspecific variation and trait-environmental relationships. These traits have to be measured on individual plants in their respective environment. Despite unprecedented data coverage, we observe a humbling lack of completeness and representativeness of these continuous traits in many aspects. We, therefore, conclude that reducing data gaps and biases in the TRY database remains a key challenge and requires a coordinated approach to data mobilization and trait measurements. This can only be achieved in collaboration with other initiatives.
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| 10. |
- Kovalev, Anton, et al.
(författare)
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Implementation approaches for 512-tap 60 GSa/s chromatic dispersion FIR filters
- 2017
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Ingår i: Conference Record of The Fifty-First Asilomar Conference on Signals, Systems & Computers. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538618233 - 9781538606667 - 9781538618240 ; , s. 1779-1783
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Konferensbidrag (refereegranskat)abstract
- In optical communication the non-ideal properties of the fibers lead to pulse widening from chromatic dispersion. One way to compensate for this is through digital signal processing. In this work, two architectures for compensation are compared. Both are designed for 60 GSa/s and 512 filter taps and implemented in the frequency domain using FFTs. It is shown that the high-speed requirements introduce constraints on possible architectural choices. Furthermore, the theoretical multiplication complexity estimates are not good predictors for the energy consumption. The results show that the implementation with 10% more multiplications per sample has half the power consumption and one third of the area consumption. The best architecture for this specification results in a power consumption of 3.12 W in a 65 nm technology, corresponding to an energy per complex filter tap of 0.10 mW/GHz.
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| 11. |
- Mohammadi Sarband, Narges, 1984-, et al.
(författare)
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Obtaining Minimum Depth Sum of Products from Multiple Constant Multiplication
- 2018
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Ingår i: PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), IEEE. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538663189 ; , s. 134-139
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Konferensbidrag (refereegranskat)abstract
- In this work, an approach for transposing solutions to the multiple constant multiplication (MCM) problem to obtain a sum of product (SOP) computation with minimum depth is proposed. The reason for doing this is that solving the SOP problem directly is highly computationally intensive when adder graph algorithms are used. Compared to using subexpression sharing algorithms, which has a lower computational complexity, directly for the SOP problem, it is shown that the proposed approach, as expected, results in lower complexity for the SOP. It is also shown that there is no obvious way to construct the MCM solution in such a way that the SOP solution has the minimum theoretical depth. However, the proposed approach guarantees minimum depth subject to the MCM solution given as input.
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| 12. |
- Sanchez, Miguel A., et al.
(författare)
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Implementing FFT-based Digital Channelized Receivers on FPGA Platforms
- 2008
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Ingår i: IEEE Transactions on Aerospace and Electronic Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9251 .- 1557-9603. ; 44:4, s. 1567-1585
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents an in-depth study of the implementationand characterization of fast Fourier transform (FFT) pipelinedarchitectures suitable for broadband digital channelized receivers.When implementing the FFT algorithm on field-programmablegate array (FPGA) platforms, the primary goal is to maximizethroughput and minimize area. Feedback and feedforwardarchitectures have been analyzed regarding key designparameters: radix, bitwidth, number of points and stage scaling.Moreover, a simplification of the FFT algorithm, the monobitFFT, has been implemented in order to achieve faster real timeperformance in broadband digital receivers. The influence ofthe hardware implementation on the performance of digitalchannelized receivers has been analyzed in depth, revealinginteresting implementation trade-offs which should be taken intoaccount when designing this kind of signal processing systems onFPGA platforms.
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