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1.	Sjöberg, Mats, 1965-, et al. (författare) Infliximab or cyclosporine as rescue therapy in hospitalized patients with steroid-refractory ulcerative colitis : a retrospective observational study 2012 Ingår i: Inflammatory Bowel Diseases. - : John Wiley & Sons. - 1078-0998 .- 1536-4844. ; 18:2, s. 212-218 Tidskriftsartikel (refereegranskat)abstract Background: Cyclosporine (CsA) or infliximab (IFX) are used as rescue therapies in steroid-refractory, severe attacks of ulcerative colitis (UC). There are no data comparing the efficacy of these two alternatives. Methods: Outcome of rescue therapy was retrospectively studied in two cohorts of patients hospitalized due to steroid-refractory moderate to severe UC: 1) a Swedish-Danish cohort (n 49) treated with a single infusion of IFX; 2) an Austrian cohort (n 43) treated with intravenous CsA. After successful rescue therapy, maintenance immunomodulator treatment was given to 27/33 (82%) of IFX patients and to 31/40 (78%) of CsA patients. Endpoints were colectomy-free survival at 3 and 12 months. Kaplan-Meier and Cox regression models were used to evaluate the association between treatment groups and colectomy. Results: At 15 days, colectomy-free survival in the IFX cohort was 36/49 (73%) versus 41/43 (95%) in the CsA cohort (P = 0.005), at 3 months 33/49 (67%) versus 40/43 (93%) (P = 0.002), and at 12 months 28/49 (57%) versus 33/43 (77%) (P = 0.034). After adjusting for potential confounding factors, Cox regression analysis yielded adjusted hazard ratios for risk of colectomy in IFX-treated patients of 11.2 (95% confidence interval [CI] 2.4-53.1, P = 0.002) at 3 months and of 3.0 (95% CI 1.1-8.2, P = 0.030) at 12 months in comparison with CsA-treated patients. There were no opportunistic infections or mortality. Conclusions: Colectomy frequencies were significantly lower after rescue therapy with CsA than with a single infusion of IFX both at 3 and 12 months' follow-up. The superiority of CsA was seen principally during the first 15 days.
2.	Andersson, Henrik (författare) Development of Process Technology for Photon Radiation Measurement Applications 2007 Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract This thesis presents work related to new types of photo detectors and their applications. The focus has been on the development of process technology and methods by means of experimentation and measurements. The overall aim has been to develop and improve photon radiation measurement applications which are possible to manufacture using standard Si processing technology. A new type of position sensitive detector that has switching possibilities based on the MOS principle has been fabricated and characterized. The influence of mechanical stress on the linearity of position sensitive detectors has been investigated. The results show that mechanical stress arising, for example, by the mounting of detectors in capsules can have an impact on device performance. Under normal circumstances these effects are rather small, but are considered to be worthwhile taking into account. Electroless deposition of Nickel including various dopants in porous silicon was performed to manufacture electrical contacts for this interesting material. After heat treatment it was confirmed by X-ray diffraction that Nickel silicide had been formed and I-V measurements show that different contacts exhibit Ohmic and rectifying behaviour. Spectrometers are used extensively in the process and food industry to measure both the chemical content and the amount of substances used during manufacturing. These instruments are often rather bulky and costly, though the trend is towards smaller and more portable equipment. A spectrometer based on an array of Fabry-Perot interferometers mounted close to an array detector is shown to be a viable option for the manufacture of a very compact device. Such a device has minimal intermediate optics and it may be possible, in the future, for it to be developed and completely integrated with a detector array into a single unit.
3.	Järnerot, Gunnar, et al. (författare) Infliximab as rescue therapy in severe to moderately severe ulcerative colitis : a randomized, placebo-controlled study. 2005 Ingår i: Gastroenterology. - : Elsevier BV. - 0016-5085 .- 1528-0012. ; 128:7, s. 1805-11 Tidskriftsartikel (refereegranskat)
4.	Witte, Anne-Barbara, et al. (författare) Involvement of endogenous glucagon-like peptide-1 in regulation of gastric motility and pancreatic endocrine secretion 2011 Ingår i: Scandinavian Journal of Gastroenterology. - : Informa UK Limited. - 0036-5521 .- 1502-7708. ; 46:4, s. 428-435 Tidskriftsartikel (refereegranskat)abstract Objective. To study the role of endogenous glucagon-like peptide-1 (GLP-1) on gastric emptying rates of a solid meal as well as postprandial hormone secretion and glucose disposal. Material and methods. In nine healthy subjects, gastric emptying of a 310-kcal radio-labelled solid meal and plasma concentrations of insulin, glucagon and glucose were measured during infusion of saline or the GLP-1 receptor antagonist exendin(9-39)amide (Ex(9-39)) at 300 pmol·kg−1·min−1. Results. Ex(9-39) infusion had no effect on the total gastric emptying curve, but changed the intra-gastric distribution of the meal. During infusion of Ex(9-39), more content stayed in the upper stomach (79.1 ± 2.5% of total during Ex(9-39) compared to 66.6 ± 5.7% during saline at 5 min). During Ex(9-39) infusion, higher concentrations of plasma glucagon were measured both before (after 40 min of Ex(9-39) infusion the glucagon level was 15.1 ± 0.7 pmol·L−1 compared to 5.4 ± 1.4 during saline) and after the meal, and postprandial GLP-1 levels increased. Basal insulin and glucose levels were not affected by Ex(9-39), but the postprandial rise of insulin and glucose enhanced during Ex(9-39). Conclusions. Endogenous GLP-1 is involved in the regulation of gastric motility in relation to meal intake and also in the regulation of postprandial insulin and glucose levels. Furthermore, endogenous GLP-1 seems to tonically restrain glucagon secretion.
5.	Abedin, Ahmad, et al. (författare) Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density 2016 Ingår i: ECS Transactions. - : Electrochemical Society. - 1938-5862 .- 1938-6737. - 9781607685395 ; , s. 615-621 Konferensbidrag (refereegranskat)abstract Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.
6.	Abedin, Ahmad, et al. (författare) Germanium on Insulator Fabrication for Monolithic 3-D Integration 2018 Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 6:1, s. 588-593 Tidskriftsartikel (refereegranskat)abstract A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.
7.	Abedin, Ahmad, et al. (författare) GOI fabrication for monolithic 3D integration 2018 Ingår i: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538637654 ; , s. 1-3 Konferensbidrag (refereegranskat)abstract A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.
8.	Abedin, Ahmad, et al. (författare) Growth of epitaxial SiGe alloys as etch-stop layers in germanium-on-insulator fabrication Annan publikation (övrigt vetenskapligt/konstnärligt)abstract In this study, the application of epitaxially grown SixGe1-x films as etch stop layers in a germanium-on-insulator substrate fabrication flow is investigated. Layers with Ge contents from 15% to 70% were epitaxially grown on Si (1 0 0) using silane and germane. It was found that the Ge content in the films is independent of the growth temperature for fixed partial pressure ratios. At low growth temperatures the activation energy is found to be 1.8 eV which points to a hydrogen desorption limited growth rate mechanism. At growth temperatures of less than 500℃, the surface roughness is <1 nm. This surface roughness does not change when the films are grown on Ge substrates. Finally, a fully strained Si0.5Ge0.5 film was grown on Ge strain relaxed buffer at 450℃. This layer demonstrates etch selectivity of >400:1 towards Ge in diluted SC-1. This result enables the integration of the Si0.5Ge0.5 film as an etch stop layer for single crystalline germanium-on-insulator substrate fabrication.
9.	Asadollahi, Ali, et al. (författare) Fabrication of relaxed germanium on insulator via room temperature wafer bonding 2014 Ingår i: ECS Transactions. - : Electrochemical Society. - 1938-6737. ; , s. 533-541 Konferensbidrag (refereegranskat)abstract We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.
10.	Asadollahi, Ali, et al. (författare) Fabrication of strained Ge on insulator via room temperature wafer bonding 2014 Ingår i: 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014. - : IEEE Computer Society. - 9781479937189 ; , s. 81-84 Konferensbidrag (refereegranskat)abstract This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si 0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).
11.	Bolten, J., et al. (författare) Fabrication of Nanowires 2014 Ingår i: Beyond CMOS Nanodevices 1. - Hoboken, NJ, USA : Wiley Blackwell. - 9781118984772 - 9781848216549 ; , s. 5-23 Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract Several fabrication processes of silicon nanowires have been developed in the research community. They can be divided into bottom-up or top-down approaches. This chapter describes top-down fabrication of silicon nanowires using electron beam lithography (EBL), which combined with optical lithography can be a viable approach if not too many silicon nanowires need to be patterned on a wafer. It also describes the sidewall transfer lithography (STL) technique using I-line stepper lithography to pattern a vast amount of silicon nanowires on a silicon wafer. In addition the chapter examines how bottom-up Si nanowires synthesized by vapor-liquid-solid (VLS)-chemical vapor deposition (CVD) can be assembled at low cost in an efficient way for further use as a sensing material. Among the solution-based assembly methods for the nanostructured network (nanonet) fabrication, the vacuum filtration method is highly simple, versatile, low cost and scalable to large areas.
12.	Bryant, Eleanor J., et al. (författare) Relationships among tonic and episodic aspects of motivation to eat, gut peptides, and weight before and after bariatric surgery 2013 Ingår i: Surgery for Obesity and Related Diseases. - : Elsevier BV. - 1550-7289 .- 1878-7533. ; 9:5, s. 802-808 Tidskriftsartikel (refereegranskat)abstract Background: The interaction between motivation to eat, eating behavior traits, and gut peptides after Roux-en-Y gastric bypass (RYGB) surgery is not fully understood. Methods: Appetite and hormone responses to a fixed liquid preload were assessed in 12 obese (body mass index 45 +/- 1.9 kg/m(2)) participants immediately before and 3 days, 2 months, and 1 year after RYGB surgery. Subjective appetite and plasma levels of ghrelin, leptin, insulin, and glucagon-like peptide-1 (GLP-1) were measured for a 3-hour postprandial period. Eating behavior traits were also measured using the Three Factor Eating Questionnaire 18 (TFEQR18). Results: There was a decrease in TFEQR18 emotional eating (EE) and uncontrolled eating (UE) from presurgery to 1 year postsurgery but no significant change in cognitive restraint (CR). These changes occurred independently of change in weight. In addition, there was a reduction in subjective appetite ratings and alterations in appetite peptides favoring an anorectic response. Presurgery EE was significantly related to fasting and area under the curve (AUC) ghrelin; UE was associated with AUC desire to eat, and there was a significant association between fasting desire to eat and ghrelin (fasting and AUC). One year postsurgery, UE was positively related to fasting insulin, and CR was negatively associated with GLP-1. UE and subjective hunger were positively correlated, while the relationship between desire to eat and ghrelin remained. onclusion: The relationships among subjective appetite ratings, eating behavior traits, and appetite peptides in obese patients both before and at 1 year after RYGB surgery may contribute to the reduction in a propensity to overeat (as measured by TFEQR18 factors) and weight loss.
13.	Capriata, Corrado Carlo Maria (författare) Dynamics and Intrinsic Variability of Spintronic Devices 2023 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract Spintronics is a scientific domain focusing on utilizing electron spin for information processing. This is the element that distinguishes it from electronics, which only utilizes the charge of electrons. A common purpose of spintronic devices is to implement additional functionalities to state-of-the-art Complementary Metal-Oxide Semiconductor (CMOS) technology. The aim of this work was to assess the intrinsic variabilities of Nano-Constriction Spin Hall Nano-Oscillators (NC-SHNOs) and the dynamics of Perpendicular Magnetic Tunnel Junctions (pMTJs). The first part of the thesis focuses on NC-SHNO and two-dimensional arrays. They are nanometer-sized microwave oscillators, allowing for a wide frequency tuning range, and are compatible with CMOS Back End Of Line (BEOL). These devices are based on a heavy metal/ferromagnetic bilayer. Environmental conditions during processing, fabrication techniques, and temperature of operation can all create variabilities in the device's functioning. Crystallization grains naturally form during the sputtering of the metals. Atomic Force Microscope (AFM) characterization showed the grains being of different shapes, about 30 nm in size. Here, the aim was to develop a simulation technique based on importing the measured grain structure into micromagnetic simulations. Their results match the device-to-device variability and multi-modal behavior found in microwave measurements. Moreover, the presence of grains influences the synchronization of the arrays.The second part of this work focuses on pMTJ. These non-volatile memory elements have two metastable states, parallel (P) and antiparallel (AP), separated by an energy barrier Eb. Here, the aim was to show their potential as True Random Number Generators (TRNGs). A pulse-activated measurement set-up was used to realize random bitstreams. The randomness was confirmed by the National Institute of Standards and Technology Statistical Testing Suite (NIST-STS). After one whitening Exclusive OR (XOR) stage, all tests were successfully passed.The assessment was completed with the development of a model describing both macrospin and domain wall-mediated magnetization reversals, i.e. switching between P and AP. The analysis of the reversal dynamics was carried out with micromagnetic simulations and String Method calculations. As expected, Eb is lowered by the field and by decreasing the device size. This allows for faster fluctuations, marking the device as a potential TRNG. Both the switching attempt frequency and the energy barrier were explored by finite-temperature micromagnetic simulations.This thesis shows the potential of realistic simulations combined with measurements to assess oscillators. It also shows the efficacy of spintronic devices as 10s-MHz TRNG.
14.	Chaourani, Panagiotis, 1989-, et al. (författare) A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors 2018 Ingår i: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). - : IEEE conference proceedings. Konferensbidrag (refereegranskat)abstract The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.
15.	Chaourani, Panagiotis, 1989-, et al. (författare) Enabling Area Efficient RF ICs through Monolithic 3D Integration 2017 Ingår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9783981537093 ; , s. 610-613 Konferensbidrag (refereegranskat)abstract The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.
16.	Chaourani, Panagiotis, et al. (författare) Inductors in a Monolithic 3-D Process : Performance Analysis and Design Guidelines 2019 Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 27:2, s. 468-480 Tidskriftsartikel (refereegranskat)abstract Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.
17.	Chaourani, Panagiotis, 1989- (författare) Sequential 3D Integration - Design Methodologies and Circuit Techniques 2019 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.
18.	Dahlgren, David, et al. (författare) Regional Intestinal Permeability of Three Model Drugs in Human 2016 Ingår i: Molecular Pharmaceutics. - : American Chemical Society (ACS). - 1543-8384 .- 1543-8392. ; 13:9, s. 3013-3021 Tidskriftsartikel (refereegranskat)abstract Currently there are only a limited number of determinations of human P-eff in the distal small intestine and none in the large intestine. This has hindered the validation of preclinical models with regard to absorption in the distal parts of the intestinal tract, which can be substantial for BCS class II-IV drugs, and drugs formulated into modified-release (MR) dosage forms. To meet this demand, three model drugs (atenolol, metoprolol, and ketoprofen) were dosed in solution intravenously, and into the jejunum, ileum, and colon of 14 healthy volunteers. The P-eff of each model drug was then calculated using a validated deconvolution method. The median P-eff of atenolol in the jejunum, ileum, and colon was 0.45, 0.15, and 0.013 X 10(-4) cm/s, respectively. The corresponding values for metoprolol were 1.72, 0.72, and 1.30 X 10(-4) cm/s, and for ketoprofen 8.85, 6.53, and 3.37 X 10(-4) cm/s, respectively. This is the first study where the human Peff of model drugs has been determined in all parts of the human intestinal tract in the same subjects. The jejunal values were similar to directly determined values using intestinal single-pass perfusion, indicating that the deconvolution method is a valid approach for determining regional P-eff. The values from this study will be highly useful in the validation of preclinical regional absorption models and in silico tools.
19.	Dentoni Litta, Eugenio, et al. (författare) Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs 2013 Ingår i: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS). - : IEEE. - 9781467348027 ; , s. 122-125 Konferensbidrag (refereegranskat)abstract The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.
20.	Dentoni Litta, Eugenio, et al. (författare) Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks 2014 Ingår i: ULIS 2014. - 9781479937189 ; , s. 69-72 Konferensbidrag (refereegranskat)abstract Integration of high-k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high-k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS-compatible process for integration of thulium silicate (TmSiO) as interfacial layer, providing advantages in terms of EOT and channel mobility. This work demonstrates the compatibility of the TmSiO/HfO2 stack with the threshold voltage control techniques commonly employed in gate-last and gate-first integration schemes, namely the use of a dual-metal process and the integration of dielectric capping layers. We show that the flatband voltage can be set from -1V to +0.5V by proper choice of gate metal, while a shift of 150-400 mV is achievable by means of integration of Al2O3 or La2O3 capping layers.
21.	Dentoni Litta, Eugenio, et al. (författare) Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology 2014 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 98, s. 20-25 Tidskriftsartikel (refereegranskat)abstract This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.
22.	Dentoni Litta, Eugenio, et al. (författare) Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs 2015 Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE conference proceedings. - 2168-6734. ; 3:5, s. 397-404 Tidskriftsartikel (refereegranskat)abstract Integration of a high-k interfacial layer (IL) is considered the leading technological solution to extend the scalability of Hf-based high-k/metal gate CMOS technology. We have previously shown that thulium silicate (TmSiO) IL can provide excellent electrical characteristics and enhanced channel mobility at sub-nm EOT. This paper presents a detailed analysis of channel mobility in TmSiO/HfO2/TiN MOSFETs, obtained through measurements at varying temperature and under constant voltage stress. We show experimentally for the first time that integration of a high-k IL can benefit mobility by attenuating remote phonon scattering. Specifically, integration of TmSiO results in attenuated remote phonon scattering compared to reference SiOx/HfO2 dielectric stacks having the same EOT, whereas it has no significant influence on remote Coulomb scattering.
23.	Dentoni Litta, Eugenio, 1986-, et al. (författare) Enhanced channel mobility by integration of sub-nm-EOT TmSiO/HfO2/TiNhigh-k/metal gate MOSFETs Annan publikation (övrigt vetenskapligt/konstnärligt)
24.	Dentoni Litta, Eugenio, et al. (författare) High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O 2013 Ingår i: Journal of the Electrochemical Society. - : The Electrochemical Society. - 0013-4651 .- 1945-7111. ; 160:11, s. D538-D542 Tidskriftsartikel (refereegranskat)abstract A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic precursor eliminates the need for a strong oxidizing agent (such as O-3) and provides a high deposition rate of similar to 1.5 angstrom/cycle. A thorough characterization of the process has been performed, identifying true ALD-type film growth in the temperature range 200-300 degrees C. The ALD process has been further investigated by extensive physical and electrical characterization of the deposited films in terms of-composition, crystalline phase, surface roughness and extraction of the dielectric constant. The films were found to be oxygen-rich Tm2O3, with low carbon impurity content at low deposition temperature and after annealing at 600 degrees C. The developed process produced polycrystalline films, with a surface roughness <1 nm RMS. Integration in MOS capacitors demonstrated well-behaved CV curves after annealing at 600 degrees C, with a relative dielectric constant of similar to 16.
25.	Dentoni Litta, Eugenio, et al. (författare) In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks 2012 Ingår i: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012. - : IEEE. - 9781467301916 ; , s. 105-108 Konferensbidrag (refereegranskat)abstract This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 A) while preserving the electrical quality of the stack.
26.	Dentoni Litta, Eugenio, 1986- (författare) Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology 2014 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes.In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of 0.25+-0.15 nm to the total EOT, and high quality of the interface with Si.Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated.The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6 nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved ~20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT.
27.	Dentoni Litta, Eugenio, et al. (författare) (Invited) TmSiO As a CMOS-Compatible High-k Dielectric 2016 Ingår i: SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 6. - : Electrochemical Society. - 9781607687146 ; , s. 79-89 Konferensbidrag (refereegranskat)abstract Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.
28.	Dentoni Litta, Eugenio, 1986-, et al. (författare) Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs 2013 Ingår i: 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC). - : IEEE Computer Society. - 9781479906499 ; , s. 155-158 Konferensbidrag (refereegranskat)abstract Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO 2/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 1013cm-2, yielding values of 180 and 75 cm2/Vs at EOT = 0.65 and 0.8 nm respectively.
29.	Dentoni Litta, Eugenio, et al. (författare) Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs 2015 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 108, s. 24-29 Tidskriftsartikel (refereegranskat)abstract High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.
30.	Dentoni Litta, Eugenio, et al. (författare) Thulium silicate interfacial layer for scalable high-k/metal gate stacks 2013 Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 60:10, s. 3271-3276 Tidskriftsartikel (refereegranskat)abstract Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.
31.	Donetti, L., et al. (författare) Hole effective mass in silicon inversion layers with different substrate orientations and channel directions 2011 Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 110:6, s. 063711- Tidskriftsartikel (refereegranskat)abstract We explore the possibility to define an effective mass parameter to describe hole transport in inversion layers in bulk MOSFETs and silicon-on-insulator devices. To do so, we employ an accurate and computationally efficient self-consistent simulator based on the six-band k . p model. The valence band structure is computed for different substrate orientations and silicon layer thicknesses and is then characterized through the calculation of different effective masses taking account of the channel direction. The effective masses for quantization and density of states are extracted from the computed energy levels and subband populations, respectively. For the transport mass, a weighted averaging procedure is introduced and justified by comparing the results with hole mobility from experiments and simulations.
32.	Donetti, L., et al. (författare) On the effective mass of holes in inversion layers 2011 Ingår i: International Conference on Ultimate Integration on Silicon. - 9781457700903 ; , s. 50-53 Konferensbidrag (refereegranskat)abstract We study hole inversion layers in bulk MOSFETs and silicon-on-insulator devices employing a self-consistent simulator based on the six-band kp model. Valence Band structure is computed for different device orientations and silicon layer thicknesses, and then it is characterized through the calculation of different effective masses.
33.	Driussi, F., et al. (författare) On the electron mobility enhancement in biaxially strained Si MOSFETs 2008 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:4, s. 498-505 Tidskriftsartikel (refereegranskat)abstract This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.
34.	Edström, Kristina, 1963-, et al. (författare) Improving student learning in STEM education: Promoting a deep approach to problem-solving Annan publikation (övrigt vetenskapligt/konstnärligt)abstract This paper addresses educational practice related to problem-solving within STEM education. A conceptual framework is shaped by conceptualising problem-solving first as an educational aim, then as a learning activity. Five principles for purposeful active learning are derived. Through this theoretical lens we investigate an active learning method called student-led recitations. In this activity students are randomly selected to present solutions to given problems, requiring them to solve the problems in advance and prepare for presenting their solutions. Drawing on the conceptual framework and informed by course results and qualitative data in the form of student interviews and teacher experiences, we analyse the teaching method. One conclusion is to challenge recitations based on teacher demonstrations of problem-solving. We suggest that student-led recitations are a cost-effective intervention, improving learning while affording more stimulating roles to both students and teachers.
35.	Ekström, Mattias, et al. (författare) Si thickness influence on subthreshold currents at high temperatures in FDSOI CMOS 2021 Ingår i: 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (EUROSOI-ULIS). - : Institute of Electrical and Electronics Engineers (IEEE). Konferensbidrag (refereegranskat)abstract Fully depleted silicon-on-insulator (FDSOI) CMOS with thick buried oxide (BOX) can operate at higher temperatures compared to bulk CMOS. This work demonstrates, both experimentally and through simulations, that the subthreshold characteristics (off-state leakage current, beak and subthreshold swing, SS) are greatly improved at high temperatures by reducing the Si thickness (t(si)) in FDSOI CMOS. Fabricated N and PFET devices exhibit low I-leak < 300 pA/mu m and close to ideal subthreshold swing (SS<132 mV/dec) at 300 degrees C. TCAD simulations closely match measured data and show that electrostatic control of the Si layer is key to achieve close to ideal SS and low I-leak. With proper gate electrodes FDSOI CMOS can achieve an I-off< 1nA/mu m at 300 degrees C for both P and NFETs. This result shows that FDSOI CMOS can find use as low power control logic at high temperatures.
36.	Eriksen, Anne Kirstine, et al. (författare) Effects of whole-grain wheat, rye, and lignan supplementation on cardiometabolic risk factors in men with metabolic syndrome: A randomized crossover trial 2020 Ingår i: American Journal of Clinical Nutrition. - : Elsevier BV. - 0002-9165 .- 1938-3207. ; 111:4, s. 864-876 Tidskriftsartikel (refereegranskat)abstract A whole-grain (WG)-rich diet has shown to have potential for both prevention and treatment of the metabolic syndrome (MetS), which is a cluster of risk factors that increase the risk of type 2 diabetes and cardiovascular disease. Different WGs may have different health effects. WG rye, in particular, may improve glucose homeostasis and blood lipids, possibly mediated through fermentable dietary fiber and lignans. Recent studies have also suggested a crucial role of the gut microbiota in response to WG. Objectives: The aim was to investigate WG rye, alone and with lignan supplements [secoisolariciresinol diglucoside (SDG)], and WG wheat diets on glucose tolerance [oral-glucose-tolerance test (OGTT)], other cardiometabolic outcomes, enterolignans, and microbiota composition. Moreover, we exploratively evaluated the role of gut microbiota enterotypes in response to intervention diets. Methods: Forty men with MetS risk profile were randomly assigned to WG diets in an 8-wk crossover study. The rye diet was supplemented with 280 mg SDG at weeks 4-8. Effects of treatment were evaluated by mixed-effects modeling, and effects on microbiota composition and the role of gut microbiota as a predictor of response to treatment were analyzed by random forest plots. Results: The WG rye diet (± SDG supplements) did not affect the OGTT compared with WG wheat. Total and LDL cholesterol were lowered (-0.06 and -0.09 mmol/L, respectively; P < 0.05) after WG rye compared with WG wheat after 4 wk but not after 8 wk. WG rye resulted in higher abundance of Bifidobacterium [fold-change (FC) = 2.58, P < 0.001] compared with baseline and lower abundance of Clostridium genus compared with WG wheat (FC = 0.54, P = 0.02). The explorative analyses suggest that baseline enterotype is associated with total and LDL-cholesterol response to diet. Conclusions: WG rye, alone or with SDG supplementation, compared with WG wheat did not affect glucose metabolism but caused transient LDL-cholesterol reduction. The effect of WG diets appeared to differ according to enterotype. This trial was registered at www.clinicaltrials.gov as NCT02987595.
37.	Fernaeus, Sven-Erik, et al. (författare) Cut the coda : early fluency intervals predict diagnoses 2008 Ingår i: Cortex. - : Elsevier BV. - 0010-9452 .- 1973-8102. ; 44:2, s. 161-169 Tidskriftsartikel (refereegranskat)abstract The aim of this study was threefold: (i) to clarify whether letter and category fluency tap different cognitive abilities; (ii) to make diagnostic comparisons and predictions using temporally resolved fluency data; (iii) to challenge and test the widely made assumption that 1-min sum scores are the fluency test measure of choice in the diagnosis of dementia. Scores from six 10-sec intervals of letter and category fluency tests were obtained from 240 participants including cognitive levels ranging from mild subjective cognitive complaints to Alzheimer's disease. Factor analysis revealed clearly separate factors corresponding to letter and category fluency. Category fluency was markedly impaired in Alzheimer's disease but not in Mild Cognitive Impairment. Only scores from relatively early intervals predicted Alzheimer's disease and Mild Cognitive Impairment. The conclusions are (i) letter and category fluency are different tests, category fluency being the best diagnostic predictor; (ii) it would be possible to administer category fluency tests only for 30 sec, because after this point the necessary differential diagnostic information about the patient's word fluency capacity has already been gathered.
38.	Fernaeus, Sven-Erik, et al. (författare) Memory factors in Rey AVLT : implications for early staging of cognitive decline 2014 Ingår i: Scandinavian Journal of Psychology. - : Wiley. - 0036-5564 .- 1467-9450. ; 55:6, s. 546-553 Tidskriftsartikel (refereegranskat)abstract Supraspan verbal list learning is widely used to assess dementia and related cognitive disorders where declarative memory deficits are a major clinical sign. While the overall learning rate is important for diagnosis, serial position patterns may give insight into more specific memory processes in patients with cognitive impairment. This study explored these patterns in a memory clinic clientele. One hundred eighty three participants took the Rey Auditory-Verbal Learning Test (RAVLT). The major groups were patients with Alzheimer's disease (AD), Vascular Dementia (VD), Mild Cognitive Impairment (MCI), and Subjective Cognitive Impairment (SCI) as well as healthy controls (HC). Raw scores for the five trials and five serial partitions were factor analysed. Three memory factors were found and interpreted as Primacy, Recency, and Resistance to Interference. AD and MCI patients had impaired scores in all factors. SCI patients were significantly impaired in the Resistance to Interference factor, and in the Recency factor at the first trial. The main conclusion is that serial position data from word list testing reflect specific memory capacities which vary with levels of cognitive impairment.
39.	Garidis, Konstantinos, 1984- (författare) Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration 2020 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract As the semiconductor industry moves beyond the 10 nm node, power consumption constraints and reduction of the negative impact of parasitic elements become important. Silicon germanium (Si1−xGex) alloys have been used to amplify the performance of Si based devices and integrated circuits (ICs) for decades. Selective epitaxial growth of heavily doped Si and/or Si1−xGex is commonly employed to reduce the effect of parasitic resistance. Reducing the supply voltage leads to lower dynamic power consumption in complementary metal-oxide-semiconductor (CMOS) technology. Monolithic three-dimensional integration (M3D) is a technology that employs vertical stacking of the device tiers. This approach reduces the wiring length, effectively reducing interconnect delay, load capacitance and ultimately reducing the power consumption. Among the integration challenges M3D is facing, one can distinguish the available thermal budget for fabrication, the crystalline quality of the device active layer and finally the actual device or circuit performance.Germanium channel devices can benefit M3D integration. Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated at significantly lower temperatures than Si. In addition, they potentially can have higher performance compared to Si due to the superior electron and hole mobilities of Ge. Active layer transfer of crystalline quality layers is a key step in a M3D fabrication flow. Direct wafer bonding techniques offerthe possibility to transfer a Ge layer on a patterned wafer. This thesis studies the various applications of Si1−xGex films in M3D. An initial implementation of an in situ doped Si1−xGex film on silicon-on-insulator (SOI) and germanium substrates is first presented. A Si1−xGex film isgrown selectively on SOI substrates to be used as a contact electrode on Si nanowire biosensors. On Ge bulk substrates, in situdoped Si1−xGex is epitaxially grown to form p+-n junctions. The junction leakage current and the mechanisms at play are studied. The analysis ofthe junction performance provides insights on the junction leakage mechanisms,an important issue for the implementation of in situ doped Si1−xGex in M3D. A low temperature germanium-on-insulator (GOI) fabrication flow based on room temperature wafer bonding and etch back is presented in this work. The method suggested in the thesis produces high quality, crystalline Ge device layers with excellent uniformity. The thesis also reports on the development and integration of Si1−xGex in the GOI fabrication as an etch stop layer, enabling the stability of the layer transfer process. Finally this thesis presents Ge p-channel field-effect transistor (PFET) devices fabricated on the previously developed GOI substrates.The technologies presented in this thesis can be integrated in large scale Ge device fabrication. The low temperature GOI and Ge PFET fabrication methods are very well suited for sequential device fabrication. The processes and applications presented in this thesis meet the current thermal budget, device performance and active layer transfer demands for M3D technology.
40.	Garidis, Konstantinos, et al. (författare) Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration 2015 Ingår i: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. - 9781479969111 ; , s. 165-168 Konferensbidrag (refereegranskat)abstract We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.
41.	Garidis, Konstantinos, et al. (författare) Selective epitaxial growth of in situ doped SiGe on bulk Ge for p+/n junction formation 2020 Ingår i: Electronics. - : MDPI AG. - 2079-9292. ; 9:4 Tidskriftsartikel (refereegranskat)abstract Epitaxial in situ doped Si0.73Ge0.27 alloys were grown selectively on patterned bulk Ge and bulk Si wafers. Si0.73Ge0.27 layers with a surface roughness of less than 3 nm were demonstrated. Selectively grown p+Si0.73Ge0.27 layers exhibited a resistivity of 3.5 mΩcm at a dopant concentration of 2.5 × 1019 boron atoms/cm3. P+/n diodes were fabricated by selectively growing p+-Si0.73Ge0.27 on n-doped bulk Ge and n-doped Si wafers, respectively. The geometrical leakage current contribution shifts from the perimeter to the bulk as the diode sizes increase. Extracted near midgap activation energies are similar to p+/n Ge junctions formed by ion implantation. This indicates that the reverse leakage current in p+/n Ge diodes fabricated with various doping methods, could originate from the same trap-assisted mechanism. Working p+/n diodes on Ge bulk substrates displayed a reverse current density as low as 2.2·10−2 A/cm2 which was found to be comparable to other literature data. The layers developed in this work can be used as an alternative method to form p+/n junctions on Ge substrates, showing comparable junction leakage results to ion implantation approaches.
42.	Garidis, Konstantinos, et al. (författare) Selective epitaxial growth of in situ doped SiGe on bulk Ge substrates forp+/n junction formation Annan publikation (populärvet., debatt m.m.)
43.	Gebart, Rikard, et al. (författare) SFC – Annual Summary from Bio4Gasification (B4G) 2020 Rapport (populärvet., debatt m.m.)
44.	Gibbons, Catherine, et al. (författare) Comparison of Postprandial Profiles of Ghrelin, Active GLP-1, and Total PYY to Meals Varying in Fat and Carbohydrate and Their Association With Hunger and the Phases of Satiety 2013 Ingår i: Journal of Clinical Endocrinology and Metabolism. - : The Endocrine Society. - 0021-972X .- 1945-7197. ; 98:5, s. E847-E855 Tidskriftsartikel (refereegranskat)abstract Context: The relationship between postprandial peptides at circulating physiological levels and short-term appetite control is not well understood. Objective: The purpose of this study was first to compare the postprandial profiles of ghrelin, glucagon-like peptide 1 (GLP-1), and peptide YY (PYY) after isoenergetic meals differing in fat and carbohydrate content and second to examine the relationships between ghrelin, GLP-1, and PYY with hunger, fullness, and energy intake. Design: Plasma was collected before and periodically after the meals for 180 minutes, after which time ad libitum food was provided. Simultaneous ratings of hunger and fullness were tracked for 180 minutes through phases identified as early (0-60 minutes) and late (60-180 minutes) satiety. Setting: This study was conducted at the Psychobiology and Energy Balance Research Unit, University of Leeds. Participants: The participants were 16 healthy overweight/obese adults. Main Outcome Measures: Changes in hunger and fullness and metabolic markers were indicators of the impact of the meals on satiety. Results: Ghrelin was influenced similarly by the 2 meals [F-(1,F- 12) = 0.658, P = .433] and was significantly associated with changes in hunger (P < .05), which in turn correlated with food intake (P < .05). GLP-1 and PYY increased more by the high-fat meal [F-(1,F- 15) = 5.099 and F-(1,F- 14) = 5.226, P < .05]. GLP-1 was negatively associated with hunger in the late satiety phase and with energy intake (P < .05), but the PYY profile was not associated with hunger or fullness, nor was PYY associated with food intake. Conclusions: The results demonstrate that under these conditions, these peptides respond differently to ingested nutrients. Ghrelin and GLP-1, but not PYY, were associated with short-term control of appetite over the measurement period.
45.	Gibbons, Catherine, et al. (författare) Postprandial profiles of CCK after high fat and high carbohydrate meals and the relationship to satiety in humans 2016 Ingår i: Peptides. - : Elsevier BV. - 0196-9781 .- 1873-5169. ; 77, s. 3-8 Tidskriftsartikel (refereegranskat)abstract CONTEXT: CCK is understood to play a major role in appetite regulation. Difficulties in measuring CCK have limited the potential to assess its profile in relation to food-induced satiety. Improvements in methodology and progress in theoretical understanding of satiety/satiation make it timely for this to be revisited.OBJECTIVE: First, examine how physiologically relevant postprandial CCK8/33(s) profiles are influenced by fat (HF) or carbohydrate (HCHO) meals. Second, to examine relationships between postprandial CCK and profiles of satiety (hunger/fullness) and satiation (meal size).PARTICIPANTS AND DESIGN: Sixteen overweight/obese adults (11 females/5 males) participated in a randomised-crossover study (46 years, 29.8kg/m(2)) in a university research centre. Plasma was collected preprandially and for 180min postprandially. Simultaneously, ratings of hunger/fullness were tracked for 180min before an ad libitum lunch was provided.RESULTS: CCK8/33(s) levels increased more rapidly and reached a higher peak following HF compared to HCHO breakfast (F(1,15)=14.737, p<0.01). Profiles of hunger/fullness did not differ between conditions (F(1,15)=0.505, p=0.488; F(1,15)=2.277, p=0.152). There was no difference in energy intake from the ad libitum meal (HF-3958 versus HCHO-3925kJ; t(14)=0.201, p=0.844). CCK8/33(s) profiles were not associated with subjective appetite during early and late phases of satiety; nor was there an association between CCK8/33(s) and meal size.CONCLUSIONS: These results demonstrate CCK levels were higher after HF meal compared to HCHO isocaloric meal. There was no association between CCK levels and intensity of satiety, or with meal size. Under these circumstances, CCK does not appear to play a unique independent role in satiety/satiation. CCK probably acts in conjunction with other peptides and the action of the stomach.
46.	Gibbons, Catherine, et al. (författare) The Role of Episodic Postprandial Peptides in Exercise-Induced Compensatory Eating 2017 Ingår i: Journal of Clinical Endocrinology and Metabolism. - : The Endocrine Society. - 0021-972X .- 1945-7197. ; 102:11, s. 4051-4059 Tidskriftsartikel (refereegranskat)abstract Context: Prolonged physical activity gives rise to variable degrees of body weight and fat loss, and is associated with variability in appetite control. Whether these effects are modulated by postprandial, peptides is unclear. We examined the role of postprandial peptide response in compensatory eating during 12 weeks of aerobic exercise and in response to high-fat, low-carbohydrate (HFLC) and low-fat, high-carbohydrate (LFHC) meals.Methods: Of the 32 overweight/obese individuals, 16 completed 12 weeks of aerobic exercise and 16 nonexercising control subjects were matched for age and body mass index. Exercisers were classified as responders or nonresponders depending on net energy balance from observed compared with expected body composition changes from measured energy expenditure. Plasma samples were collected before and after meals to compare profiles of total and acylated ghrelin, insulin, cholecystokinin, glucagon-like peptide 1 (GLP-1), and total peptide YY (PYY) between HFLC and LFHC meals, pre- and postexercise, and between groups.Results: No differences between pre- and postintervention peptide release. Responders had greater suppression of acylated ghrelin (P < 0.05) than nonresponders, as well as higher postprandial levels of GLP-1 (P < 0.001) and total PYY (P < 0.001) compared with nonresponders and control subjects.Conclusion: No impact on postprandial peptide release was found after 12 weeks of aerobic exercise. Responders to exercise-induced weight loss showed greater suppression of acylated ghrelin and greater release of GLP-1 and total PYY at baseline. Therefore, episodic postprandial peptide profiles appear to form part of the pre-existing physiology of exercise responders and suggest differences in satiety potential may underlie exercise-induced compensatory eating.
47.	Gomeniuk, Y. Y., et al. (författare) Electrical properties of high-k LaLuO3 gate oxide for SOI MOSFETs 2011 Ingår i: 6th International Workshop on Semiconductor-on-Insulator Materials and Devices. - 9783037851784 ; , s. 87-93 Konferensbidrag (refereegranskat)abstract The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-? LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO 3/Si interface is presented and typical maxima of 1.2×10 11 eV-1cm-2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 μm and 50 μm, respectively) are presented. The front channel mobility appeared to be 126 cm2V -1s-1 and 70 cm2V-1s-1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.
48.	Gudmundsson, Valur, et al. (författare) Characterization of dopant segregated Schottky barrier source/drain contacts 2009 Ingår i: ULIS 2009. - NEW YORK : IEEE. - 9781424437054 ; , s. 73-76 Konferensbidrag (refereegranskat)abstract In this paper, the gate-voltage dependent source/drain (S/D) resistance (R-SD) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced by a highly doped shallow layer in Si or by an interfacial dipole causing SB height lowering. The simulation reveals that the gate-voltage dependence of R-SD is stronger for the dipole effect. For the SB-MOSFETs with DS-S/D examined in this work, the simulation gives an excellent fit to the measured data when SBH lowering is combined with high concentration shallow doping.
49.	Gudmundsson, Valur, et al. (författare) Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM 2008 Ingår i: PROCEEDINGS OF THE 17TH INTERNATIONAL VACUUM CONGRESS/13TH INTERNATIONAL CONFERENCE ON SURFACE SCIENCE/INTERNATIONAL CONFERENCE ON NANOSCIENCE AND TECHNOLOGY. - Bristol : IOP PUBLISHING LTD. Konferensbidrag (refereegranskat)abstract In this paper the effect of the commonly used HBr/Cl-2 chemistry for dry etching on the line-edge roughness (LER) of photoresist patterned single crystalline Si (sc-Si), polycrystalline Si (poly-Si) and poly-Si0.2Ge0.8 sidewalls was characterized. Measurements were done by means of atomic force microscopy in combination with an elaborated sample preparation technique that allowed the LER at different depths of the sidewall to be measured. Samples were patterned by I-line lithography and etching was performed at an RF power of 200 W using HBr/Cl-2 (30/10 sccm) plasma. For sc-Si the photoresist and Si sidewalls had an LER of 0.8-1.4 nm and 1.5-2 nm, respectively. For poly-Si and poly-SiGe the photoresist sidewall roughness was, respectively, increased to 1.5-3 nm and 2-3.5 nm due to light scattering from the rough surface of the polycrystalline materials. The poly-Si film had a sidewall roughness of 3-4 nm. Poly-SiGe sidewall exhibited larger roughness with an LER of 5-12 nm which was not transferred from the photoresist. The results show that for sc-Si and poly-Si the sidewall roughness mainly originates from the photoresist process and little additional roughening is caused by the HBr/Cl-2 etching. However, for poly-Si0.2Ge0.8 the LER is considerably increased from that of the photoresist indicating that the HBr/Cl-2 etching is the main contributor to the LER.
50.	Gudmundsson, Valur, et al. (författare) Effect of Be segregation on NiSi/Si Schottky barrier heights 2011 Ingår i: Solid-State Device Research Conference (ESSDERC). - 9781457707070 - 9781457707063 Konferensbidrag (refereegranskat)abstract The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process. The SBH modulation was found to be strongly dependent on the silicidation temperature, with a minimum barrier to the valence band Φbp=0.28±0.02 eV, for diodes formed at 600 °C. SIMS analysis show the Be dose left at the interface is very low. With such a low dose, modulation cannot be caused by an interface dipole. However, the results can be explained assuming a thin (~4-5 nm) layer of activated Be close to the interface.

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