| 1. |
- Sjöberg, Mats, 1965-, et al.
(författare)
-
Infliximab or cyclosporine as rescue therapy in hospitalized patients with steroid-refractory ulcerative colitis : a retrospective observational study
- 2012
-
Ingår i: Inflammatory Bowel Diseases. - : John Wiley & Sons. - 1078-0998 .- 1536-4844. ; 18:2, s. 212-218
-
Tidskriftsartikel (refereegranskat)abstract
- Background: Cyclosporine (CsA) or infliximab (IFX) are used as rescue therapies in steroid-refractory, severe attacks of ulcerative colitis (UC). There are no data comparing the efficacy of these two alternatives. Methods: Outcome of rescue therapy was retrospectively studied in two cohorts of patients hospitalized due to steroid-refractory moderate to severe UC: 1) a Swedish-Danish cohort (n 49) treated with a single infusion of IFX; 2) an Austrian cohort (n 43) treated with intravenous CsA. After successful rescue therapy, maintenance immunomodulator treatment was given to 27/33 (82%) of IFX patients and to 31/40 (78%) of CsA patients. Endpoints were colectomy-free survival at 3 and 12 months. Kaplan-Meier and Cox regression models were used to evaluate the association between treatment groups and colectomy. Results: At 15 days, colectomy-free survival in the IFX cohort was 36/49 (73%) versus 41/43 (95%) in the CsA cohort (P = 0.005), at 3 months 33/49 (67%) versus 40/43 (93%) (P = 0.002), and at 12 months 28/49 (57%) versus 33/43 (77%) (P = 0.034). After adjusting for potential confounding factors, Cox regression analysis yielded adjusted hazard ratios for risk of colectomy in IFX-treated patients of 11.2 (95% confidence interval [CI] 2.4-53.1, P = 0.002) at 3 months and of 3.0 (95% CI 1.1-8.2, P = 0.030) at 12 months in comparison with CsA-treated patients. There were no opportunistic infections or mortality. Conclusions: Colectomy frequencies were significantly lower after rescue therapy with CsA than with a single infusion of IFX both at 3 and 12 months' follow-up. The superiority of CsA was seen principally during the first 15 days.
|
|
| 2. |
- Abedin, Ahmad, et al.
(författare)
-
Germanium on Insulator Fabrication for Monolithic 3-D Integration
- 2018
-
Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 6:1, s. 588-593
-
Tidskriftsartikel (refereegranskat)abstract
- A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.
|
|
| 3. |
- Abedin, Ahmad, et al.
(författare)
-
GOI fabrication for monolithic 3D integration
- 2018
-
Ingår i: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538637654 ; , s. 1-3
-
Konferensbidrag (refereegranskat)abstract
- A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.
|
|
| 4. |
- Abedin, Ahmad, et al.
(författare)
-
Growth of epitaxial SiGe alloys as etch-stop layers in germanium-on-insulator fabrication
-
Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- In this study, the application of epitaxially grown SixGe1-x films as etch stop layers in a germanium-on-insulator substrate fabrication flow is investigated. Layers with Ge contents from 15% to 70% were epitaxially grown on Si (1 0 0) using silane and germane. It was found that the Ge content in the films is independent of the growth temperature for fixed partial pressure ratios. At low growth temperatures the activation energy is found to be 1.8 eV which points to a hydrogen desorption limited growth rate mechanism. At growth temperatures of less than 500℃, the surface roughness is <1 nm. This surface roughness does not change when the films are grown on Ge substrates. Finally, a fully strained Si0.5Ge0.5 film was grown on Ge strain relaxed buffer at 450℃. This layer demonstrates etch selectivity of >400:1 towards Ge in diluted SC-1. This result enables the integration of the Si0.5Ge0.5 film as an etch stop layer for single crystalline germanium-on-insulator substrate fabrication.
|
|
| 5. |
- Capriata, Corrado Carlo Maria
(författare)
-
Dynamics and Intrinsic Variability of Spintronic Devices
- 2023
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Spintronics is a scientific domain focusing on utilizing electron spin for information processing. This is the element that distinguishes it from electronics, which only utilizes the charge of electrons. A common purpose of spintronic devices is to implement additional functionalities to state-of-the-art Complementary Metal-Oxide Semiconductor (CMOS) technology. The aim of this work was to assess the intrinsic variabilities of Nano-Constriction Spin Hall Nano-Oscillators (NC-SHNOs) and the dynamics of Perpendicular Magnetic Tunnel Junctions (pMTJs). The first part of the thesis focuses on NC-SHNO and two-dimensional arrays. They are nanometer-sized microwave oscillators, allowing for a wide frequency tuning range, and are compatible with CMOS Back End Of Line (BEOL). These devices are based on a heavy metal/ferromagnetic bilayer. Environmental conditions during processing, fabrication techniques, and temperature of operation can all create variabilities in the device's functioning. Crystallization grains naturally form during the sputtering of the metals. Atomic Force Microscope (AFM) characterization showed the grains being of different shapes, about 30 nm in size. Here, the aim was to develop a simulation technique based on importing the measured grain structure into micromagnetic simulations. Their results match the device-to-device variability and multi-modal behavior found in microwave measurements. Moreover, the presence of grains influences the synchronization of the arrays.The second part of this work focuses on pMTJ. These non-volatile memory elements have two metastable states, parallel (P) and antiparallel (AP), separated by an energy barrier Eb. Here, the aim was to show their potential as True Random Number Generators (TRNGs). A pulse-activated measurement set-up was used to realize random bitstreams. The randomness was confirmed by the National Institute of Standards and Technology Statistical Testing Suite (NIST-STS). After one whitening Exclusive OR (XOR) stage, all tests were successfully passed.The assessment was completed with the development of a model describing both macrospin and domain wall-mediated magnetization reversals, i.e. switching between P and AP. The analysis of the reversal dynamics was carried out with micromagnetic simulations and String Method calculations. As expected, Eb is lowered by the field and by decreasing the device size. This allows for faster fluctuations, marking the device as a potential TRNG. Both the switching attempt frequency and the energy barrier were explored by finite-temperature micromagnetic simulations.This thesis shows the potential of realistic simulations combined with measurements to assess oscillators. It also shows the efficacy of spintronic devices as 10s-MHz TRNG.
|
|
| 6. |
- Chaourani, Panagiotis, 1989-, et al.
(författare)
-
A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors
- 2018
-
Ingår i: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). - : IEEE conference proceedings.
-
Konferensbidrag (refereegranskat)abstract
- The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.
|
|
| 7. |
- Chaourani, Panagiotis, et al.
(författare)
-
Inductors in a Monolithic 3-D Process : Performance Analysis and Design Guidelines
- 2019
-
Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 27:2, s. 468-480
-
Tidskriftsartikel (refereegranskat)abstract
- Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.
|
|
| 8. |
- Chaourani, Panagiotis, 1989-
(författare)
-
Sequential 3D Integration - Design Methodologies and Circuit Techniques
- 2019
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.
|
|
| 9. |
- Dentoni Litta, Eugenio, et al.
(författare)
-
(Invited) TmSiO As a CMOS-Compatible High-k Dielectric
- 2016
-
Ingår i: SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 6. - : Electrochemical Society. - 9781607687146 ; , s. 79-89
-
Konferensbidrag (refereegranskat)abstract
- Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.
|
|
| 10. |
- Edström, Kristina, 1963-, et al.
(författare)
-
Improving student learning in STEM education: Promoting a deep approach to problem-solving
-
Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- This paper addresses educational practice related to problem-solving within STEM education. A conceptual framework is shaped by conceptualising problem-solving first as an educational aim, then as a learning activity. Five principles for purposeful active learning are derived. Through this theoretical lens we investigate an active learning method called student-led recitations. In this activity students are randomly selected to present solutions to given problems, requiring them to solve the problems in advance and prepare for presenting their solutions. Drawing on the conceptual framework and informed by course results and qualitative data in the form of student interviews and teacher experiences, we analyse the teaching method. One conclusion is to challenge recitations based on teacher demonstrations of problem-solving. We suggest that student-led recitations are a cost-effective intervention, improving learning while affording more stimulating roles to both students and teachers.
|
|
| 11. |
- Ekström, Mattias, et al.
(författare)
-
Si thickness influence on subthreshold currents at high temperatures in FDSOI CMOS
- 2021
-
Ingår i: 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (EUROSOI-ULIS). - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- Fully depleted silicon-on-insulator (FDSOI) CMOS with thick buried oxide (BOX) can operate at higher temperatures compared to bulk CMOS. This work demonstrates, both experimentally and through simulations, that the subthreshold characteristics (off-state leakage current, beak and subthreshold swing, SS) are greatly improved at high temperatures by reducing the Si thickness (t(si)) in FDSOI CMOS. Fabricated N and PFET devices exhibit low I-leak < 300 pA/mu m and close to ideal subthreshold swing (SS<132 mV/dec) at 300 degrees C. TCAD simulations closely match measured data and show that electrostatic control of the Si layer is key to achieve close to ideal SS and low I-leak. With proper gate electrodes FDSOI CMOS can achieve an I-off< 1nA/mu m at 300 degrees C for both P and NFETs. This result shows that FDSOI CMOS can find use as low power control logic at high temperatures.
|
|
| 12. |
- Garidis, Konstantinos, 1984-
(författare)
-
Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration
- 2020
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- As the semiconductor industry moves beyond the 10 nm node, power consumption constraints and reduction of the negative impact of parasitic elements become important. Silicon germanium (Si1−xGex) alloys have been used to amplify the performance of Si based devices and integrated circuits (ICs) for decades. Selective epitaxial growth of heavily doped Si and/or Si1−xGex is commonly employed to reduce the effect of parasitic resistance. Reducing the supply voltage leads to lower dynamic power consumption in complementary metal-oxide-semiconductor (CMOS) technology. Monolithic three-dimensional integration (M3D) is a technology that employs vertical stacking of the device tiers. This approach reduces the wiring length, effectively reducing interconnect delay, load capacitance and ultimately reducing the power consumption. Among the integration challenges M3D is facing, one can distinguish the available thermal budget for fabrication, the crystalline quality of the device active layer and finally the actual device or circuit performance.Germanium channel devices can benefit M3D integration. Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated at significantly lower temperatures than Si. In addition, they potentially can have higher performance compared to Si due to the superior electron and hole mobilities of Ge. Active layer transfer of crystalline quality layers is a key step in a M3D fabrication flow. Direct wafer bonding techniques offerthe possibility to transfer a Ge layer on a patterned wafer. This thesis studies the various applications of Si1−xGex films in M3D. An initial implementation of an in situ doped Si1−xGex film on silicon-on-insulator (SOI) and germanium substrates is first presented. A Si1−xGex film isgrown selectively on SOI substrates to be used as a contact electrode on Si nanowire biosensors. On Ge bulk substrates, in situdoped Si1−xGex is epitaxially grown to form p+-n junctions. The junction leakage current and the mechanisms at play are studied. The analysis ofthe junction performance provides insights on the junction leakage mechanisms,an important issue for the implementation of in situ doped Si1−xGex in M3D. A low temperature germanium-on-insulator (GOI) fabrication flow based on room temperature wafer bonding and etch back is presented in this work. The method suggested in the thesis produces high quality, crystalline Ge device layers with excellent uniformity. The thesis also reports on the development and integration of Si1−xGex in the GOI fabrication as an etch stop layer, enabling the stability of the layer transfer process. Finally this thesis presents Ge p-channel field-effect transistor (PFET) devices fabricated on the previously developed GOI substrates.The technologies presented in this thesis can be integrated in large scale Ge device fabrication. The low temperature GOI and Ge PFET fabrication methods are very well suited for sequential device fabrication. The processes and applications presented in this thesis meet the current thermal budget, device performance and active layer transfer demands for M3D technology.
|
|
| 13. |
- Garidis, Konstantinos, et al.
(författare)
-
Selective epitaxial growth of in situ doped SiGe on bulk Ge for p+/n junction formation
- 2020
-
Ingår i: Electronics. - : MDPI AG. - 2079-9292. ; 9:4
-
Tidskriftsartikel (refereegranskat)abstract
- Epitaxial in situ doped Si0.73Ge0.27 alloys were grown selectively on patterned bulk Ge and bulk Si wafers. Si0.73Ge0.27 layers with a surface roughness of less than 3 nm were demonstrated. Selectively grown p+Si0.73Ge0.27 layers exhibited a resistivity of 3.5 mΩcm at a dopant concentration of 2.5 × 1019 boron atoms/cm3. P+/n diodes were fabricated by selectively growing p+-Si0.73Ge0.27 on n-doped bulk Ge and n-doped Si wafers, respectively. The geometrical leakage current contribution shifts from the perimeter to the bulk as the diode sizes increase. Extracted near midgap activation energies are similar to p+/n Ge junctions formed by ion implantation. This indicates that the reverse leakage current in p+/n Ge diodes fabricated with various doping methods, could originate from the same trap-assisted mechanism. Working p+/n diodes on Ge bulk substrates displayed a reverse current density as low as 2.2·10−2 A/cm2 which was found to be comparable to other literature data. The layers developed in this work can be used as an alternative method to form p+/n junctions on Ge substrates, showing comparable junction leakage results to ion implantation approaches.
|
|
| 14. |
|
|
| 15. |
- Hou, Shuoben, et al.
(författare)
-
4H-SiC PIN diode as high temperature multifunction sensor
- 2017
-
Ingår i: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016. - : Trans Tech Publications Ltd. - 9783035710434 ; , s. 630-633
-
Konferensbidrag (refereegranskat)abstract
- An in-house fabricated 4H-SiC PIN diode that has both optical sensing and temperature sensing functions from room temperature (RT) to 550 ºC is presented. The two sensing functions can be simply converted from one to the other by switching the bias voltage on the diode. The optical responsivity of the diode at 365 nm is 31.8 mA/W at 550 ºC. The temperature sensitivity of the diode is 2.7 mV/ºC at the forward current of 1 μA.
|
|
| 16. |
- Hou, Shuoben, et al.
(författare)
-
A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode
- 2019
-
Ingår i: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 40:1, s. 51-54
-
Tidskriftsartikel (refereegranskat)abstract
- This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.
|
|
| 17. |
- Hou, Shuoben, et al.
(författare)
-
A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C
- 2020
-
Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 8:1, s. 116-121
-
Tidskriftsartikel (refereegranskat)abstract
- An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.
|
|
| 18. |
- Hou, Shuoben, et al.
(författare)
-
High Temperature High Current Gain IC Compatible 4H-SiC Phototransistor
- 2019
-
Konferensbidrag (refereegranskat)abstract
- This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 ºC. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 ºC. The βFmax drops to 51 at 400 ºC and remains the same at 500 ºC. The photo current gain of the phototransistor is 3.9 at 25 ºC and increases to 14 at 500 ºC under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4HSiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics onchip integration.
|
|
| 19. |
- Hou, Shuoben, et al.
(författare)
-
Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits
- 2019
-
Ingår i: Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019. - : IEEE.
-
Konferensbidrag (refereegranskat)abstract
- Processing techniques for 4H-SiC devices and circuits are optimized. The SiC mesa etching process has a variation of < 5% over the wafer. The average n-type contact resistivity is 1.15 × 10-6 Ohm.cm2. The fabricated devices and circuits with one-layer metal interconnect have high yield with no need of chemical-mechanical planarization process. More complex circuits with two-layer metal interconnect achieve high yield by applying chemical-mechanical planarization process.
|
|
| 20. |
- Hou, Shuoben, et al.
(författare)
-
Scaling and modeling of high temperature 4H-SiC p-i-n photodiodes
- 2018
-
Ingår i: IEEE Journal of the Electron Devices Society. - : Institute of Electrical and Electronics Engineers Inc.. - 2168-6734. ; 6:1, s. 139-145
-
Tidskriftsartikel (refereegranskat)abstract
- 4H-SiC p-i-n photodiodes with various mesa areas (40,000μm2, 2500μm2, 1600μm2, and 400μm2) have been fabricated. Both C-V and I-V characteristics of the photodiodes have been measured at room temperature, 200 °C, 400 °C, and 500 °C. The capacitance and photo current (at 365 nm) of the photodiodes are directly proportional to the area. However, the dark current density increases as the device is scaled down due to the perimeter surface recombination effect. The photo to dark current ratio at the full depletion voltage of the intrinsic layer (-2.7 V) of the photodiode at 500 °C decreases 7 times as the size of the photodiode scales down 100 times. The static and dynamic behavior of the photodiodes are modeled with SPICE parameters at the four temperatures.
|
|
| 21. |
- Hou, Shuoben
(författare)
-
Silicon Carbide High Temperature Photodetectors and Image Sensor
- 2019
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Silicon Carbide (SiC) has the advantages of ultraviolet (UV) sensing and high temperature characteristics because of its wide band gap. Both merits make SiC photodetectors very attractive in astronomy, oil drilling, combustion detection, biology and medical applications. Driven by the objective of probing the high temperature surface of Venus (460 °C), this thesis develops SiC photodetectors and an image sensor for extremely high temperature functions. The devices and circuits are demonstrated through the procedure of layout design, in-house processing and characterizations on two batches.The process flow has been optimized to be suitable for large scale integration (LSI) of SiC bipolar integrated circuits (IC). The improved processing steps are SiC dry etching, ohmic contacts and two-level metal interconnect with chemical-mechanical polishing (CMP). The optimized process flow is applied in the fabrication of discrete devices, a transistor-transistor logic (TTL) process design kit (PDK) and LSI circuits.The photodetectors developed in this thesis, including photodiodes with various mesa areas, a phototransistor and a phototransistor Darlington pair have stable characteristics in a wide temperature range (25 °C ~ 500 °C). The maximum operational temperature of the p-i-n photodiode (550 °C) is the highest recorded temperature accomplished ever by a photodiode. The optical responsivity of the photodetectors covers the spectrum from 220 nm to 380 nm, which is UV-only.The SiC pixel sensor and image sensor developed in this thesis are pioneer works. The pixel sensor overcomes the challenge of monolithic integration of SiC photodiode and transistors by sharing the same epitaxial layers and topside contacts. The pixel sensor is characterized from 25 °C to 500 °C. The whole image sensor circuit has 256 (16 ×16) pixel sensors and one 8-bit counter together with two 4-to-16 decoders for row/column selection. The digital circuits are built by the standard logic gates selected from the TTL PDK. The image sensor has 1959 transistors in total. The function of the image sensor up to 400 °C is verified by taking basic photos of nonuniform UV illumination on the pixel sensor array.This thesis makes an important attempt on the demonstration of SiC opto-electronic on-chip integration. The results lay a foundation on the development of future high temperature high resolution UV image sensors.
|
|
| 22. |
- Jablonka, Lukas, et al.
(författare)
-
Formation of nickel germanides from Ni layers with thickness below 10 nm
- 2017
-
Ingår i: Journal of Vacuum Science & Technology B. - : A V S AMER INST PHYSICS. - 1071-1023 .- 1520-8567. ; 35:2
-
Tidskriftsartikel (refereegranskat)abstract
- The authors have studied the reaction between a Ge (100) substrate and thin layers of Ni ranging from 2 to 10 nm in thickness. The formation of metal-rich Ni5Ge3 was found to precede that of the monogermanide NiGe by means of real-time in situ x-ray diffraction during ramp-annealing and ex situ x-ray pole figure analyses for phase identification. The observed sequential growth of Ni5Ge3 and NiGe with such thin Ni layers is different from the previously reported simultaneous growth with thicker Ni layers. The phase transformation from Ni5Ge3 to NiGe was found to be nucleationcontrolled for Ni thicknesses < 5 nm, which is well supported by thermodynamic considerations. Specifically, the temperature for the NiGe formation increased with decreasing Ni (rather Ni5Ge3) thickness below 5 nm. In combination with sheet resistance measurement and microscopic surface inspection of samples annealed with a standard rapid thermal processing, the temperature range for achieving morphologically stable NiGe layers was identified for this standard annealing process. As expected, it was found to be strongly dependent on the initial Ni thickness.
|
|
| 23. |
- Jayakumar, Ganesh, et al.
(författare)
-
Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application
- 2018
-
Ingår i: Micromachines. - : MDPI. - 2072-666X. ; 9:11
-
Tidskriftsartikel (refereegranskat)abstract
- Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (V-G) and backgate voltage (V-BG). The liquid potential can be monitored using the FG. We report the transfer characteristics (I-D-V-G) of N- and P-type SiRi pixels. Further, the I-D-V-G characteristics of the SiRis are studied at different V-BG. The application of V-BG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (V-TH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large V-BG (25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large V-BG to switch ON. Thus, P-type pixels exhibit excellent I-ON/I-OFF 10(6), SS of 70-80 mV/dec and V-TH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.
|
|
| 24. |
- Jayakumar, Ganesh, 1987-
(författare)
-
Silicon nanowire based devices for More than Moore Applications
- 2018
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. While the recent research has concentrated predominantly on utilizing single or multiple SiNW for biosensing applications, very few attempts have been made to integrate SiNW with complementary-metal-oxide- semiconductor (CMOS) integration to arrive at a complete lab-on-chip (LOC) sensor. Further, the manufacturing methods reported thus far in the production of SiNW for biosensing applications have not fully exploited both the front-end-of-line (FEOL) as well as back-end-of-line (BEOL) methods in CMOS integration. Neither does the research community address CMOS integration based methods to realize multi and specific target detection that are important attributes for an ideal LOC biosensor.Integration of SiNW with CMOS circuitry will facilitate real time detection of the output signal and in addition provide a compact small sized sensor that is fully portable operating at high speed. In order to avail the benefits of CMOS circuits and develop a large scale production friendly LOC sensor, the scheme of SiNW fabrication has to facilitate either the FEOL or BEOL CMOS integration schemes. This thesis work is focused on revealing a novel FEOL as well as BEOL scheme for integration of SiNW with CMOS circuitry. The major part of the FEOL research work is concentrated on developing a high volume SiNW manufacturing method that is suitable for industrial production. Likewise, in the BEOL scheme, predominant focus was to develop a wafer scale scheme to integrate network of nanowires (nanonets) with CMOS circuitry to manufacture a monolithic 3D above-IC LOC biosensor.In the FEOL scheme, the SiNWs are fabricated using a revised pattern transfer technique called sidewall transfer lithography (STL). The STL method is identified as one of the efficient methods of fabricating SiNW as it uses CMOS industry grade materials that is fully compatible with the FEOL fabrication scheme. Thanks to the usage of single lithography and controlled selective etching techniques used in the STL process, the line width and aspect ratio of the SiNW can be tailored to suit the requirements for DNA hybridization detection. A fabrication process flow matching standard CMOS process integration flows has been developed to integrate SiNW with HfO2 and TiN metal gate MOSFETS. An emphasis has been placed in the design of a novel pixel matrix based SiNW LOC sensor. Specific and multi-target detection has been kept as top priority in the design of the SiNW LOC sensor. The possibility to monitor the potential of the electrolyte during the detection process using a fluid gate has been accounted in this design. Furthermore, the SiNW pixel design eliminates the intricate microfluidics and eases access to the SiNW test site using a simple photolithography mask and RIE. The SiNW and MOSFETS demonstrate excellent electrical characteristics. For the very first time, the concept to access single as well as multiple array SiNW pixels using a transistor has been successfully demonstrated.In the BEOL scheme, the nanonets are fabricated using the bottom-up method and transferred onto a pre-fabricated CMOS wafer supplied by ams foundry. The connection between the nanonets lying above-IC and the underlying CMOS layer was established by employing a thin metal backgate electrode, backgate dielectric and metal source/drain contact pads. Many challenges in the BEOL scheme have been identified and overcome by incorporating efficient device architecture and careful selection of materials. To the first of its kind, a wafer scale process was developed to integrate nanonets with CMOS to form a monolithic 3D IC. The devices exhibit excellent electrical characteristics and lower leakage currents compared to standalone nanonet sensors fabricated on Si/SiN substrate. Further, the FEOL and BEOL integration schemes are compared and the various pro’s and con’s of both approaches for integration of SiNW with CMOS circuits to build a LOC biosensor are discussed in detail.Finally, dry environment DNA hybridization detection is demonstrated on the surface of thin HfO2 encapsulated SiNW sensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bio-processes. More specifically, based on a statistical analysis, it is demonstrated that 85% of the tested devices were efficient for DNA hybridization detection. The estimated density of hybridized DNA was in the order of 1010 cm-2. These promising results of realizing a SiNW based lab-on-chip platform through the FEOL and BEOL monolithic integration of SiNW and CMOS circuitry further strengthen the profile of SiNW as a nano biosensor. Indeed, this is expected to pave the way for more than Moore applications of SiNW based devices and integrated circuits.
|
|
| 25. |
- Jayakumar, Ganesh, et al.
(författare)
-
Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors
- 2019
-
Ingår i: Microelectronic Engineering. - : Elsevier B.V.. - 0167-9317 .- 1873-5568. ; 212, s. 13-20
-
Tidskriftsartikel (refereegranskat)abstract
- Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.
|
|
| 26. |
- Jayakumar, Ganesh, et al.
(författare)
-
Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment
- 2019
-
Ingår i: Nanotechnology. - : NLM (Medline). - 0957-4484 .- 1361-6528. ; 30:18
-
Tidskriftsartikel (refereegranskat)abstract
- Silicon nanowire (SiNW) charge based biosensors are attractive for DNA sensing applications due to their compactness and large surface-to-volume ratio. Small feature size, low production cost, repeatability, high sensitivity and selectivity are some of the key requirements for biosensors. The most common e-beam manufacturing method employed to manufacture sub-nm SiNWs is both cost and time intensive. Therefore, we propose a highly reproducible CMOS industry grade low-cost process to fabricate SiNW-based field effect transistors on 4-wafers. The 60 nm wide SiNWs reported in this paper are fabricated using the sidewall transfer lithography process which is a self-aligned-double-patterning I-line lithography process that also facilitates encapsulation of the SiNW surface with a thin HfO2 layer on which DNA probes are grafted to finalize the biosensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bioprocesses. More specifically, based on a statistical analysis, we demonstrate that 85% of the tested devices exhibit a positive threshold voltage shift after DNA hybridization. These promising results make way for the monolithic integration of SiNW biosensors and CMOS circuitry to realize a point of care device which can offer reliable real time electrical readout.
|
|
| 27. |
- Lindskog, Henrik, 1977, et al.
(författare)
-
New insights to vascular smooth muscle cell and pericyte differentiation of mouse embryonic stem cells in vitro.
- 2006
-
Ingår i: Arteriosclerosis, thrombosis, and vascular biology. - 1524-4636. ; 26:7, s. 1457-64
-
Tidskriftsartikel (refereegranskat)abstract
- OBJECTIVE: The molecular mechanisms that regulate pericyte differentiation are not well understood, partly because of the lack of well-characterized in vitro systems that model this process. In this article, we develop a mouse embryonic stem (ES) cell-based angiogenesis/vasculogenesis assay and characterize the system for vascular smooth muscle cell (VSMC) and pericyte differentiation. METHODS AND RESULTS: ES cells that were cultured for 5 days on OP9 stroma cells upregulated their transcription of VSMC and pericyte selective genes. Other SMC marker genes were induced at a later time point, which suggests that vascular SMC/pericyte genes are regulated by a separate mechanism. Moreover, sequence analysis failed to identify any conserved CArG elements in the vascular SMC and pericyte gene promoters, which indicates that serum response factor is not involved in their regulation. Gleevec, a tyrosine kinase inhibitor that blocks platelet-derived growth factor (PDGF) spell-receptor signaling, and a neutralizing antibody against transforming growth factor (TGF) beta1, beta2, and beta3 failed to inhibit the induction of vascular SMC/pericyte genes. Finally, ES-derived vascular sprouts recruited cocultured MEF cells to pericyte-typical locations. The recruited cells activated expression of a VSMC- and pericyte-specific reporter gene. CONCLUSIONS: We conclude that OP9 stroma cells induce pericyte differentiation of cocultured mouse ES cells. The induction of pericyte marker genes is temporally separated from the induction of SMC genes and does not require platelet-derived growth factor B or TGFbeta1 signaling.
|
|
| 28. |
- Olyaei, Maryam, et al.
(författare)
-
Low-frequency Noise in High-k LaLuO3/TiN MOSFETs
- 2011
-
Ingår i: 2011 International Semiconductor Device Research Symposium (ISDRS). ; , s. TA01-TA04
-
Konferensbidrag (refereegranskat)abstract
- The implementation of high-k gate stacks has enabled further scaling in CMOS technology. However it is still challenging due to increased number of trap densities appeared at the high-k interface or in the bulk, mobility degradation and enhancement in the level of low-frequency noise [1]. Previously low-frequency noise in devices with PtSi Schottky-barrier source/drain contacts were studied [2]. In this work the low-frequency noise characterization of MOSFETs with high-k LaLuO3 dielectric and TiN gate is presented. The devices were fabricated on an SOI substrate thinned down to 30 nm by sacrificial dry oxidation and HF wet etching. Active areas were patterned through MESA etching. The process was continued with an optional growth of a 5 nm layer of thermal oxide on the wafers. The high-k LaLuO3 dielectric was deposited by MBE (tLaLuO3=6 nm) and the metal TiN gate by sputtering (tTiN=20 nm). This was followed by in-situ deposition of phosphorus doped poly-Si with tpoly=150 nm. For the reference wafer, the high-k deposition was skipped. PtSi Schottky-barrier source/drain with Boron and Arsenic implantation was carried out for pMOSFETs and nMOSFETs respectively. In the next step, RTA at 700°C was performed for dopant segregation at the PtSi/Si interface. The fabrication process was finalized by metallization and FGA (10% H2 in N2 at 400° C for 30 min).
|
|
| 29. |
- Olyaei, Maryam, et al.
(författare)
-
Low-Frequency Noise in High-k LaLuO3/TiN MOSFETs
- 2012
-
Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 78:SI, s. 51-55
-
Tidskriftsartikel (refereegranskat)abstract
- Low-frequency noise (LFN) characterization of high-k LaLuO3/TiN nMOS transistors is presented. The experimental results including the noise spectrum and normalized power noise density and mobility are reported. The noise results were successfully modeled to the correlated number and mobility fluctuation noise equation. High-k dielectric devices show lower mobility and roughly one to two orders of magnitude higher low-frequency noise which is comparable to the hafnium based oxide layers. The implementation of higher-k LaLuO3 seems to be a suitable candidate to the trade-off between equivalent oxide thickness scaling and low frequency noise.
|
|
| 30. |
- Ramos Santesmases, David, et al.
(författare)
-
1/f Noise and Dark Current Correlation in Midwave InAs/GaSb Type-II Superlattice IR Detectors
- 2021
-
Ingår i: Physica Status Solidi (a) applications and materials science. - : Wiley-VCH Verlag. - 1862-6300 .- 1862-6319. ; 218:3, s. 2000557-
-
Tidskriftsartikel (refereegranskat)abstract
- Herein, results from noise and dark current density studies on InAs/GaSb type-II superlattice IR detectors are presented. The activation energy of the dark current density is used to identify the dominating dark current mechanisms (generation–recombination (GR), tunneling, or diffusion dark current) as a function of temperature and bias. The bias evolution of the power spectral density (PSD) is measured in dark conditions for several temperatures. At the operating bias of the detectors, the arrays show a white noise–dominated spectrum up to 100 K with a minor 1/f contribution (corner frequency around 10 Hz), while for higher temperatures the spectra are 1/f dominated. The 1/f noise component is compared to the dominating dark current mechanism in the same temperature and bias regimes. A strong correlation between the 1/f noise component and the dominating dark current (I) is found, with the PSD proportional to I for tunneling currents and I2 for GR and diffusion currents. Very low noise coefficients of αGR = 4.8 × 10−9 Hz−1, αdiff = 1.9 × 10−10 Hz−1, and αtun = 2.1 × 10−16 A Hz−1 are observed for these detectors.
|
|
| 31. |
- Ramos Santesmases, David, et al.
(författare)
-
Optical concentration in fully delineated mid-wave infrared T2SL detectors arrays
- 2023
-
Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 123:18
-
Tidskriftsartikel (refereegranskat)abstract
- The dependence of quantum efficiency (QE) on fill factor and pixel pitch is studied theoretically and experimentally in fully delineated type-II superlattice (T2SL) detectors. Theoretically, a 2-dimensional simulation model is used to compute the absorption in the array geometry, which shows an insensitivity of the optical response to the fill factor. This is a result of the photodiode array (PDA) geometry concentrating the light in the pixel area. QE measurements on PDAs with varying pixel pitch (from 225 to 10 μm) and fill factors (from 98% to 64%) confirm this independence of the QE on the fill factor and results in a 50% increase in the photocurrent density in 10 μm pitch PDAs compared to 225 μm pitch PDAs. Furthermore, measurements of the dark current density vs pixel size revealed an absence of surface leakage in these PDAs, which, combined with the increased photocurrent density results in an improved signal-to-noise ratio when reducing the pitch in these T2SL detectors. Finally, this result resolves the QE-modulation transfer function trade-off, as the electrical isolation of the pixel is carried out without impacting the QE of the array.
|
|
| 32. |
- Ramos Santesmases, David
(författare)
-
Process development of III-V-based infrared detectors
- 2024
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Type-II Superlattice (T2SL) detectors have revolutionized the field of infraredimaging, establishing themselves as the forefront technology in defense, space,and industrial applications. These detectors enable larger formats and higheroperating temperatures (HOT) that minimize the need for bulky and energyconsumingcryogenic cooling, paving the way for imaging systems with reducedSize, Weight, and Power (SWaP).Their versatility across various IR wavebands—long-wavelength, midwavelength,and extended short-wavelength—combined with the intrinsicscalability characteristic of III-V detectors, positions T2SL technology as the idealchoice for next-generation HOT and high-resolution (HD) detectors.This thesis focuses on improving the manufacturing process for T2SL arrays toreduce surface leakage currents induced during pixel etching. This challengebecomes more pronounced with smaller pixels and directly affects the maximumoperating temperature.The investigation into T2SL detector performance provides comprehensiveinsights into the detectors' electrical characteristics. This includes 1/f noiseanalysis and a detailed experimental and quantitative modeling of surface leakagecurrents, proposing strategies for their reduction. Furthermore, the study delvesinto light-matter interactions within focal plane arrays (FPAs) to describe opticalconcentration effects to increase the sensitivity and provides Modulation transferfunction measurements and simulations to discuss the resolution of T2SL arrays.Employing diverse Sb-based T2SL detector photodiode structures, this thesisreports significant progress in the fabrication process, leading to remarkableachievements. These include the demonstration and industrial production of a640 × 512 – 15 μm format FPA operating at 150 K; the production of 10, 7.5,and 5 μm pitch arrays, all capable of functioning at 150 K; and the demonstrationof small-pitch HD FPAs, with the capability of operating at 150K.
|
|
| 33. |
- Ramos Santesmases, David, et al.
(författare)
-
Quasi-3-dimensional simulations and experimental validation of surface leakage currents in high operating temperature type-II superlattice infrared detectors
- 2022
-
Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 132:20, s. 204501-
-
Tidskriftsartikel (refereegranskat)abstract
- The surface leakage in InAs/GaSb type-II superlattice (T2SL) is studied experimentally and theoretically for photodiodes with small sizes down to 10 x 10 mu m(2). The dependence of dark current density on mesa size is studied at 110 and 200 K, and surface leakage is shown to impact both generation-recombination (GR) and diffusion dark current mechanisms. A quasi-3-dimensional model to simulate the fabrication process using surface traps on the pixel's sidewall is presented and is used to accurately represent the dark current of large and small pixels with surface leakage in the different temperature regimes. The simulations confirmed that the surface leakage current has a GR and diffusion component at low and high temperature, respectively. Finally, the surface leakage current has been correlated with the change in minority carrier concentration at the surface due to the presence of donor traps.
|
|
| 34. |
- Ramos Santesmases, David, et al.
(författare)
-
Simulation and Characterization of the Modulation Transfer Function in Fully Delineated Type-II Superlattices Infrared Detectors
- 2024
-
Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9383 .- 1557-9646. ; 71:4, s. 2459-2464
-
Tidskriftsartikel (refereegranskat)abstract
- The modulation transfer function (MTF) in fully delineated 15 μ m pitch type-II superlattice (T2SL) mid-wave infrared (IR) detectors is studied theoretically and experimentally. Theoretically, a 2-D model to simulate the spot scan (SS) profile is presented and used to compute the MTF as a function of the wavelength and the array geometry (pitch size, trench width). The dependence of the detector trench on the MTF is also evaluated experimentally by the edge spread function (ESF) method according to the ISO12233 standard. The experimental results show an excellent agreement with the theoretical model, reporting an MTF of 0.61 and 0.60 at the Nyquist frequency for 1 and 2 μ m trench, respectively. With the simulation model, the effect of the increased optical crosstalk for smaller pixel pitch is discussed as a function of the trench width (0.5, 1, and 2 μ m) and incidence angle up to ± 30 ∘ . Simulation results show MTF values at the Nyquist frequency between 0.61–0.62, 0.58–0.60, and 0.55–0.57 with an average degradation of 1%, 2%, and 7% at an angle of ± 30 ∘ compared to normal incidence for the 10, 7.5, and 5 μ m pitch, respectively.
|
|
| 35. |
- Ramos Santesmases, David, et al.
(författare)
-
Two-step etch in n-on-p type-II superlattices for surface leakage reduction in mid-wave infrared megapixel detectors
- 2023
-
Ingår i: Opto-Electronics Review. - : Polish Academy of Sciences Chancellery. - 1230-3402 .- 1896-3757. ; 31:1
-
Tidskriftsartikel (refereegranskat)abstract
- This work investigates the potential of p-type InAs/GaSb superlattice for the fabrication of full mid-wave megapixel detectors with n-on-p polarity. A significantly higher surface leakage is observed in deep-etched n-on-p photodiodes compared to p-on-n diodes. Shallow-etch and two-etch-step pixel geometry are demonstrated to mitigate the surface leakage on devices down to 10 mu m with n-on-p polarity. A lateral diffusion length of 16 mu m is extracted from the shallow etched pixels, which indicates that cross talk could be a major problem in small pitch arrays. Therefore, the two-etch-step process is used in the fabrication of 1280 x 1024 arrays with a 7.5 mu m pitch, and a potential operating temperature up to 100 K is demonstrated.
|
|
| 36. |
- Ungaro, Ryan C., et al.
(författare)
-
Deep Remission at 1 Year Prevents Progression of Early Crohn's Disease
- 2020
-
Ingår i: Gastroenterology. - : W. B. Saunders Company. - 0016-5085 .- 1528-0012. ; 159:1, s. 139-147
-
Tidskriftsartikel (refereegranskat)abstract
- BACKGROUND & AIMS: We investigated the effects of inducing deep remission in patients with early Crohn's disease (CD).METHODS: We collected follow-up data from 122 patients (mean age, 31.2 ± 11.3 y) with early, moderate to severe CD (median duration, 0.2 years; interquartile range, 0.1-0.5) who participated in the Effect of Tight Control Management on CD (CALM) study, at 31 sites, representing 50% of the original CALM patient population. Fifty percent of patients (n = 61) were randomly assigned to a tight control strategy (increased therapy based on fecal level of calprotectin, serum level of C-reactive protein, and symptoms), and 50% were assigned to conventional management. We categorized patients as those who were vs were not in deep remission (CD endoscopic index of severity scores below 4, with no deep ulcerations or steroid treatment, for 8 or more weeks) at the end of the follow-up period (median, 3.02 years; range, 0.05-6.26 years). The primary outcome was a composite of major adverse outcomes that indicate CD progression during the follow-up period: new internal fistulas or abscesses, strictures, perianal fistulas or abscesses, or hospitalization or surgery for CD. Kaplan-Meier and penalized Cox regression with bootstrapping were used to compare composite rates between patients who achieved or did not achieve remission at the end of the follow-up period.RESULTS: Major adverse outcomes were reported for 34 patients (27.9%) during the follow-up period. Significantly fewer patients in deep remission at the end of the CALM study had major adverse outcomes during the follow-up period (P = .01). When we adjusted for potential confounders, deep remission (adjusted hazard ratio, 0.19; 95% confidence interval, 0.07-0.31) was significantly associated with a lower risk of major adverse outcome.CONCLUSIONS: In an analysis of follow-up data from the CALM study, we associated induction of deep remission in early, moderate to severe CD with decreased risk of disease progression over a median time of 3 years, regardless of tight control or conventional management strategy.
|
|
| 37. |
- Vallejo-Perez, Monica, et al.
(författare)
-
Optimization of GOPS-Based Functionalization Process and Impact of Aptamer Grafting on the Si Nanonet FET Electrical Properties as First Steps towards Thrombin Electrical Detection
- 2020
-
Ingår i: Nanomaterials. - : MDPI. - 2079-4991. ; 10:9
-
Tidskriftsartikel (refereegranskat)abstract
- Field effect transistors (FETs) based on networks of randomly oriented Si nanowires (Si nanonets or Si NNs) were biomodified using Thrombin Binding Aptamer (TBA-15) probe with the final objective to sense thrombin by electrical detection. In this work, the impact of the biomodification on the electrical properties of the Si NN-FETs was studied. First, the results that were obtained for the optimization of the (3-Glycidyloxypropyl)trimethoxysilane (GOPS)-based biofunctionalization process by using UV radiation are reported. The biofunctionalized devices were analyzed by atomic force microscopy (AFM) and scanning transmission electron microscopy (STEM), proving that TBA-15 probes were properly grafted on the surface of the devices, and by means of epifluorescence microscopy it was possible to demonstrate that the UV-assisted GOPS-based functionalization notably improves the homogeneity of the surface DNA distribution. Later, the electrical characteristics of 80 devices were analyzed before and after the biofunctionalization process, indicating that the results are highly dependent on the experimental protocol. We found that the TBA-15 hybridization capacity with its complementary strand is time dependent and that the transfer characteristics of the Si NN-FETs obtained after the TBA-15 probe grafting are also time dependent. These results help to elucidate and define the experimental precautions that must be taken into account to fabricate reproducible devices.
|
|
| 38. |
- Zurauskaite, Laura
(författare)
-
Ge/high-k Gates for Monolithic 3D Integration
- 2021
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation.In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for Si-cap growth conditions. Selected gate stacks with GeOx and Si-cap passivation have been integrated in Ge pFET process on in-house fabricated germanium on insulator substrates. Subthreshold slope values inline with previous reports have been achieved, as well as 60 % higher hole mobility than in reference silicon on insulator pFETs. Moreover, initial results of Si-cap and TmSiO interfacial layer integration ingermanium on insulator nFETs have been demonstrated.This work presents both advantages and limitations of each gate stacksolution on Ge platform. The processes employed in this work are monolithic 3D integration compatible, and demonstrate that with some process optimization Ge transistors could be integrated on Si platform in monolithic3D integration fashion.
|
|
| 39. |
- Zurauskaite, Laura, et al.
(författare)
-
Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal
- 2021
-
Ingår i: IEEE 51ST EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2021). - : IEEE. ; , s. 227-230
-
Konferensbidrag (refereegranskat)abstract
- The improvement of forming gas anneal (10 % H-2 in N-2) at 400 degrees C on electrical properties of Ge/GeOx/Tm2O3/HfO2 gate stacks is investigated. It is found that forming gas anneal effectively suppresses fixed charge density, oxide trap density and interface state density. Hydrogen is demonstrated to efficiently passivate the negative fixed charge density and reduce the global variability of the Hatband voltage down to 90 mV over a safer. A forming gas anneal is also found to reduce equivalent oxide thickness in scaled gate stacks.
|
|
| 40. |
- Zurauskaite, Laura, et al.
(författare)
-
Investigation of Tm2O3 as a gate dielectric for Ge MOS devices
- 2018
-
Ingår i: ECS Transactions. - : Electrochemical Society. - 1938-5862. ; , s. 67-73
-
Konferensbidrag (refereegranskat)abstract
- In this work atomic layer deposited Tm2O3 has been investigated as a high-k dielectric for Ge-based gate stacks. It is shown that when Tm2O3 is deposited on high-quality Ge/GeO2 gates, the interface state density of the gate stack is degraded. A series of post-deposition anneals are studied in order to improve the interface state density of Ge/GeOx/Tm2O3 gates, and it is demonstrated that a rapid thermal anneal in O2 ambient can effectively reduce the interface state density to below 5-1011 cm-2eV-1 without increasing the equivalent oxide thickness. Fixed charge density in Ge/GeOx/Tm2O3 gates has also been investigated, and it is shown that while O2 post-deposition anneal improves the interface state density, the fixed charge density is degraded.
|
|
| 41. |
- Zurauskaite, Laura, et al.
(författare)
-
Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer
- 2020
-
Ingår i: ECS Journal of Solid State Science and Technology. - : The Electrochemical Society. - 2162-8769 .- 2162-8777. ; 9:12
-
Tidskriftsartikel (refereegranskat)abstract
- In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 degrees C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for D-it < 510(11) cm(-2) eV(-1). Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 310(11) eV(-1) cm(-2) and a significant improvement in oxide trap density compared to GeOx passivation.
|
|
| 42. |
- Zurauskaite, Laura, et al.
(författare)
-
Si-passivated Ge Gate stacks with low interface state and oxide trap densities using thulium silicate
- 2020
-
Ingår i: ECS Transactions. - : IOP Publishing Ltd. - 1938-5862 .- 1938-6737. ; , s. 387-393
-
Konferensbidrag (refereegranskat)abstract
- Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks.
|
|
| 43. |
- Zurauskaite, Laura, et al.
(författare)
-
The impact of atomic layer depositions on high quality Ge/GeO2 interfaces fabricated by rapid thermal annealing in O2 ambient
- 2017
-
Ingår i: 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509046607 ; , s. 164-166
-
Konferensbidrag (refereegranskat)abstract
- This work demonstrates high quality Ge/GeO2 interfaces fabricated by O2 RTA that are degraded by a good quality SiO2 layer deposited by ALD. However, neither O3 and H2O precursors commonly used during subsequent high-k ALDs nor Si precursor AP-LTO-330 do not degrade the interface. Thus Dit increase after SiO2 deposition is likely due to intermixing. Therefore, the effect of subsequent ALDs on the interface quality has to be considered while designing Ge-based gate stacks.
|
|
| 44. |
- Östling, Mikael, et al.
(författare)
-
Technology challenges in silicon devices beyond the 16 nm node
- 2011
-
Ingår i: Proceedings of the 18th International Conference. - 9788393207503 ; , s. 27-31
-
Konferensbidrag (refereegranskat)abstract
- An overview of metallic source/drain (MSD) contacts in nano-scaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nano-scaled CMOS, i.e. extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier height (SBH), S/D to gate underlap, top Si layer thickness, oxide thickness should be optimized. Recently, efforts have been invested in MSD MOSFETs based on Pt- and Ni-silicide implementation and several promising results have been reported in literature. The experimental work as well as the results of Monte Carlo simulations by several investigators, including the authors, is discussed in this paper. It will be shown that the present results place MSD MOSFETs as a competitive candidate for future generations of CMOS technology.
|
|
| 45. |
- Östling, Mikael, et al.
(författare)
-
Three-Dimensional Integration of Ge and Two-Dimensional Materials for One-Dimensional Devices
- 2016
-
Ingår i: Future Trends in Microelectronics: Journey into the Unknown. - Hoboken, NJ, USA : wiley. - 9781119069225 - 9781119069119 ; , s. 51-67
-
Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- This chapter focuses primarily on sequential 3D, since only the high interconnection density achieved in this case is capable of supporting a scaling path in the vertical dimension. The successful implementation of a sequential 3D integration scheme requires a strong research effort in developing low-thermal-budget front-end of line (FEOL) processing. The chapter summarizes the status of current research in FEOL processing compatible with sequential 3D integration, as well as a view of the main outstanding challenges. It explores the possibility of integrating novel concepts based on 2D materials. In addition, sequential 3D integration has a strong impact not only at the device level but also at the system level, requiring the development of a 3D design ecosystem. In conclusion, one can observe that the technological foundation for sequential 3D integration is almost in place, since great progress has been made to develop low-thermal-budget processing and integration of novel materials.
|
|
