| 1. |
- Arghavani, Abbas, et al.
(author)
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Power-Adaptive Communication With Channel-Aware Transmission Scheduling in WBANs
- 2024
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In: IEEE Internet of Things Journal. - : Institute of Electrical and Electronics Engineers (IEEE). - 2327-4662. ; 11:9, s. 16087-16102
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Journal article (peer-reviewed)abstract
- Radio links in wireless body area networks (WBANs) are highly subject to short and long-term attenuation due to the unstable network topology and frequent body blockage. This instability makes it challenging to achieve reliable and energy-efficient communication, but on the other hand, provides a great potential for the sending nodes to dynamically schedule the transmissions at the time with the best expected channel quality. Motivated by this, we propose improved Gilbert-Elliott Markov chain model (IGE), a memory-efficient Markov chain model to monitor channel fluctuations and provide a long-term channel prediction. We then design adaptive transmission power selection (ATPS), a deadline-constrained channel scheduling scheme that enables a sending node to buffer the packets when the channel is bad and schedule them to be transmitted when the channel is expected to be good within a deadline. ATPS can self-learn the pattern of channel changes without imposing a significant computation or memory overhead on the sending node. We evaluate the performance of ATPS through experiments using TelosB motes under different scenarios with different body postures and packet rates. We further compare ATPS with several state-of-the-art schemes, including the optimal scheduling policy, in which the optimal transmission time for each packet is calculated based on the collected received signal strength indicator (RSSI) samples in an off-line manner. The experimental results reveal that ATPS performs almost as efficiently as the optimal scheme in high-date-rate scenarios and has a similar trend on power level usage.
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| 2. |
- Arslan, Mehmet Ali, et al.
(author)
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Programming support for reconfigurable custom vector architectures
- 2015
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In: Proc. PPoPP, Principles and Practice of Parallel Programming. - New York, NY, USA : ACM. - 9781450334044 ; , s. 49-57
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Conference paper (peer-reviewed)abstract
- High performance requirements increased the popularity of unconventional architectures. While providing better performance, such architectures are generally harder to program and generate code for. In this paper, we present our approach to ease programmability and code generation for such architectures. We present a domain specific language (DSL) for the programming part, and a constraint programming approach to scheduling with memory allocation. Our experiments on implementing a kernel extracted from a DSP appli- cation on an example reconfigurable custom architecture shows that it is possible to achieve performance close to hand-written machine code that is scheduled without memory allocation.
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