| 1. |
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| 2. |
- Guang, Liang, et al.
(författare)
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Hierarchical Agent Monitored Parallel On-Chip System : A Novel Design Paradigm and its Formal Specification
- 2010
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Ingår i: International Journal of Embedded and Real-Time Communication Systems (IJERTCS). - : IGI Global. - 1947-3176 .- 1947-3184. ; 1:2, s. 86-105
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the authors present a formal specification of a novel design paradigm, hierarchical agent monitored SoCs (HAMSOC). The paradigm motivates dynamic monitoring in a hierarchical and distributed manner, with adaptive agents embedded for local and global operations. Formal methods are of essential importance to the development of such a novel and complex platform. As the initial effort, functional specification is indispensable to the non-ambiguous system modeling before potential property verification. The formal specification defines the manner by which the system can be constructed with hierarchical components and the representation of run-time information in modeling entities and every type of the monitoring operations. The syntax follows the standard set theory with additional glossary and notations introduced to facilitate practical SoC design process. A case study of hierarchical monitoring for power management in NoC (Network-on-chip), written with the formal specification, is demonstrated
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| 3. |
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| 4. |
- Guang, Liang, et al.
(författare)
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Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
- 2010
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Ingår i: ACM Transactions on Embedded Computing Systems. - : Association for Computing Machinery (ACM). - 1539-9087 .- 1558-3465. ; 9:3
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Tidskriftsartikel (refereegranskat)abstract
- Hierarchical agent framework is proposed to construct a monitoring layer towards self-aware parallel systems-on-chip (SoCs). With monitoring services as a new design dimension, systems are capable of observing and reconfiguring themselves dynamically at all levels of granularity, based on application requirements and platform conditions. Agents with hierarchical priorities work adaptively and cooperatively to maintain and improve system performance in the presence of variations and faults. Function partitioning of agents and hierarchical monitoring operations on parallel SoCs are analyzed. Applying the design approach on the Network-on-Chip (NoC) platform demonstrates the design process and benefits using the novel approach.
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| 5. |
- Guang, Liang, et al.
(författare)
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Hierarchical Agent Monitoring Design Platform - towards Self-aware and Adaptive Embedded Systems
- 2011
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Ingår i: PECCS 2011 - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems. ; , s. 573-581
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Konferensbidrag (refereegranskat)abstract
- Hierarchical agent monitoring design platform(HAM) is presented as a generic design approach for the emerging self-aware and adaptive embedded systems. Such systems, with various existing proposals for different advanced features, call for a concrete, practical and portable design approach. HAM addresses this necessity by providing a scalable and generically applicable design platform. This paper elaborately describes the hierarchical agent monitoring architecture, with extensive reference to the state-of-the-art technology in embedded systems. Two case studies are exemplified to demonstrate the design process and benefits of HAM design platform. One is about hierarchical agent monitored Network-on-Chip with quantitative experiments of hierarchical energy management. The other one is a projectional study of applying HAM on smart house systems, focusing on the design for enhanced dependability.
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| 6. |
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| 7. |
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| 8. |
- Guang, Liang, et al.
(författare)
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Interconnection alternatives for hierarchical monitoring communication in parallel SoCs
- 2010
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Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 34:5, s. 118-128
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Tidskriftsartikel (refereegranskat)abstract
- Interconnection architectures for hierarchical monitoring communication in parallel System-on-Chip (SoC) platforms are explored. Hierarchical agent monitoring design paradigm is an efficient and scalable approach for the design of parallel embedded systems. Between distributed agents on different levels, monitoring communication is required to exchange information, which forms a prioritized traffic class over data traffic. The paper explains the common monitoring operations in SoCs, and categorizes them into different types of functionality and various granularities. Requirements for on-chip interconnections to support the monitoring communication are outlined. Baseline architecture with best-effort service, time division multiple access (TDMA) and two types of physically separate interconnections are discussed and compared, both theoretically and quantitatively on a Network-on-Chip (NoC)-based platform. The simulation uses power estimation of 65 nm technology and NoC microbenchmarks as traffic traces. The evaluation points out the benefits and issues of each interconnection alternative. In particular, hierarchical monitoring networks are the most suitable alternative, which decouple the monitoring communication from data traffic, provide the highest energy efficiency with simple switching, and enable flexible reconfiguration to tradeoff power and performance.
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| 9. |
- Guang, Liang, et al.
(författare)
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Low-latency and Energy-efficient Monitoring Interconnect for Hierarchical-agent-monitored NoCs
- 2008
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Ingår i: Norchip - 26th Norchip Conference, Formal Proceedings. - 9781424424931 ; , s. 227-232
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Konferensbidrag (refereegranskat)abstract
- This paper presents quantitative analysis of monitoring interconnect architecture alternatives in hierarchical agent-based NoC platform. Hierarchical monitoring design methodology provides scalable dynamic management services with agents monitoring different levels. To enable low-latency and lowenergy agent communication, we examined three interconnect alternatives: TDM-based virtual channeling, unified dedicated monitoring network, and separate dedicated monitoring networks. With Orion and Cadence simulators, we estimated the energy and latency of monitoring communications on the three architectures for an 8*8 mesh network in 65nm technology. The results suggest that separate dedicate links mostly minimize the communication delay and energy consumption (66.7% and 82.1% respectively compared to TDM-based interconnect), while incurring moderate area penalty.
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| 10. |
- Hellberg, Lars, et al.
(författare)
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System oriented VLSI curriculum at KTH
- 1997
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Ingår i: ; , s. 57-59
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Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products
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| 11. |
- Hemani, Ahmed, et al.
(författare)
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A structure of modern VLSI curriculum
- 1994
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Ingår i: ; , s. 204-208
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Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at Royal Institute of Technology, Sweden. Changing needs of industry, advances in technology and design methodology has required a significant reorganisation of VLSI education with emphasis on system issues. This restructuring is not viewed as a one step process, rather as a continuous process including close interaction between education and research
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| 12. |
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Interconnect-centric design for advanced SoC and NoC
- 2005
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Samlingsverk (redaktörskap) (refereegranskat)abstract
- In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.
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| 13. |
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| 14. |
- Isoaho, Jouni, et al.
(författare)
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High level synthesis in DSP ASIC optimization
- 1994
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Ingår i: Proc. of 7th IEEE ASIC Conference and Exhibit. ; , s. 75-78
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Konferensbidrag (refereegranskat)abstract
- In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples
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| 15. |
- Isoaho, Jouni, et al.
(författare)
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HLS based DSP optimization with ASIC RTL libraries
- 1994
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Ingår i: ; , s. 218-225
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Konferensbidrag (refereegranskat)abstract
- In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach
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| 16. |
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| 17. |
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| 18. |
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| 19. |
- Rahimi Moosavi, Sanaz, et al.
(författare)
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SEA : A Secure and Efficient Authentication and Authorization Architecture for IoT-Based Healthcare Using Smart Gateways
- 2015
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Ingår i: Procedia Computer Science. - : Elsevier. - 1877-0509. ; 52, s. 452-459
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a secure and efficient authentication and authorization architecture for IoT-based healthcare is developed. Security and privacy of patients’ medical data are crucial for the acceptance and ubiquitous use of IoT in healthcare. Secure authentication and authorization of a remote healthcare professional is the main focus of this work. Due to resource constraints of medical sensors, it is infeasible to utilize conventional cryptography in IoT-based healthcare. In addition, gateways in existing IoTs focus only on trivial tasks without alleviating the authentication and authorization challenges. In the presented architecture, authentication and authorization of a remote end-user is done by distributed smart e-health gateways to unburden the medical sensors from performing these tasks. The proposed architecture relies on the certificate-based DTLS handshake protocol as it is the main IP security solution for IoT. The proposed authentication and authorization architecture is tested by developing a prototype IoT-based healthcare system. The prototype is built of a Pandaboard, a TI SmartRF06 board and WiSMotes. The CC2538 module integrated into the TI board acts as a smart gateway and the WisMotes act as medical sensor nodes. The proposed architecture is more secure than a state-of-the-art centralized delegation-based architecture because it uses a more secure key management scheme between sensor nodes and the smart gateway. Furthermore, the impact of DoS attacks is reduced due to the distributed nature of the architecture. Our performance evaluation results show that compared to the delegation-based architecture, the proposed architecture reduces communication overhead by 26% and communication latency from the smart gateway to the end-user by 16%.
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| 20. |
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| 21. |
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| 22. |
- Shen, Meigen, et al.
(författare)
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Concurrent chip-package design for 10GHz global clock distribution network
- 2005
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Ingår i: 55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings. - 0780389069 ; , s. 1554-1559
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Konferensbidrag (refereegranskat)abstract
- As a result of the continuous downscaling of the CMOS technology, on chip frequency for high performance microprocessor will soon arrive 10GHz according to international technology roadmap for semiconductors (ITRS). In this paper, a 10GHz global clock distribution network using standing wave approach was analyzed on chip and package level. On chip level, a 10GHz standing wave oscillator (SWO) for global clock distribution network using 0.18um, 1P6M CMOS technology, is designed and analyzed. The simulation results show that the skew is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On package level, we assume that the chip size is 20mm*20mm and flip-chip bonding technology is used. The simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of tau(clk) when the attenuation is about 1.5dB. For attenuation from 1.5dB to 6.7dB, the peak positions (n*lambda/2) can be used as clock node. For the mesh and plane shape, the skew is controlled within 10% of tau(clk) using standing wave method.
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| 23. |
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| 24. |
- Tuuna, S., et al.
(författare)
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Analysis of delay variation in encoded on-chip bus signaling under process variation
- 2008
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Ingår i: 21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN. - 9780769530833 ; , s. 228-234
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Konferensbidrag (refereegranskat)abstract
- In this paper we model on-chip signaling over a bus consisting of encoding, drivers, transmission lines, receivers and decoding. We characterize the signaling circuitry as a function of its load capacitance. The effective load capacitance seen by a driver is derived for the decoupling method and distributed RLC transmission line models. The driver delay and rise time corresponding to the derived effective capacitance are used to derive the far-end voltage of a transmission line bus. The effects of process variation are taken into account in the characterization of the signaling circuitry and in the wire analysis. The overall delay variation of the bus due to device and wire process variation is then calculated. The model is verified by comparing it to HSPICE. We implement regular voltage mode, level-encoded dual-rail and 1-of-4 signaling circuitry and apply the derived model to analyze them. The implementation and analysis are done in 45 nm technology.
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| 25. |
- Tuuna, Sampo, et al.
(författare)
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Modeling of on-chip bus switching current and its impact on noise in power supply grid
- 2008
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 16:6, s. 766-770
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance-inductance-capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.
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| 26. |
- Öberg, Johnny, et al.
(författare)
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A rule-based approach for improving allocation of filter structures in HLS
- 1996
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Ingår i: Ninth International Conference on VLSI Design, 1996. Proceedings. - : IEEE conference proceedings. - 0818672285 ; , s. 133-139
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Konferensbidrag (refereegranskat)abstract
- A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designers knowledge about the design class. Experiments also indicate that employing direct mapping of CDFG subgraphs onto preoptimised RTL-level macroblocks would have resulted in a relative area gain of 500%. The macroblock had only 16% of the area produced by the HLS-tool
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