| 1. |
- Mattavelli, Marco, et al.
(författare)
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MPEG reconfigurable video coding
- 2018
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Ingår i: Handbook of Signal Processing Systems. - Cham : Springer International Publishing. - 9783319917337 - 9783319917344 ; , s. 213-249
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Bokkapitel (refereegranskat)abstract
- The current monolithic and lengthy scheme behind the standardization and the design of new video coding standards is becoming inappropriate to satisfy the dynamism and changing needs of the video coding community. Such a scheme and specification formalism do not enable designers to exploit the clear commonalities between the different codecs, neither at the level of the specification nor at the level of the implementation. Such a problem is one of the main reasons for the typical long time interval elapsing between the time a new idea is validated until it is implemented in consumer products as part of a worldwide standard. The analysis of this problem originated a new standard initiative within the ISO/IEC MPEG committee, called Reconfigurable Video Coding (RVC). The main idea is to develop a video coding standard that overcomes many shortcomings of the current standardization and specification process by updating and progressively incrementing a modular library of components. As the name implies, flexibility and reconfigurability are new attractive features of the RVC standard. The RVC framework is based on the usage of a new actor/dataflow oriented language called CAL for the specification of the standard library and the instantiation of the RVC decoder model. CAL dataflow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. This chapter gives an overview of the concepts and technologies building the standard RVC framework and the non standard tools supporting the RVC model from the instantiation and simulation of the CAL model to the software and/or hardware code synthesis.
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| 2. |
- Savas, Suleyman, et al.
(författare)
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Generating hardware and software for RISC-V cores generated with Rocket Chip generator
- 2021
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Ingår i: Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021. - 2164-1676 .- 2164-1706. - 9781665429313 ; 2021-September, s. 89-94
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Konferensbidrag (refereegranskat)abstract
- This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow description of an algorithm as input and generates a combination of hardware (in Chisel) and software (in C) that interacts with the hardware. The hardware can be integrated with RISC-V cores created by the Rocket Chip generator and the software can be executed on these cores.The generated hardware requires similar amount of resources as the hand-written hardware while achieving equal or higher clock rates. As expected, the accelerators perform the calculations faster than the general purpose processor, 5 to 33x in our experiments. When these accelerators are integrated with the Rocket cores, they increase the performance by 25% and 260% in the two use-cases we investigate.
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| 3. |
- Schurmann, Jonathan, et al.
(författare)
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Crystal centering using deep learning in X-ray crystallography
- 2020
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Ingår i: 2019 53rd Asilomar Conference on Signals, Systems, and Computers. - 9781728143019 - 9781728143002 ; , s. 978-983
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Konferensbidrag (refereegranskat)abstract
- A key challenge in X-ray crystallography is to find a good point on the crystal on which to center the beam because the crystal takes radiation damage after a number of shots which significantly distort the measurements. Therefore, the beam needs to be aimed manually by an operator, which results in significant additional effort and time.This paper presents an approach toward automating the beam aiming using machine learning, training a neural network with labeled data, resulting in a more efficient system that does not rely on manual supervision to determine where to aim the beam. A range of different neural network architectures are evaluated based on the accuracy of their predictions.
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