| 1. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
Theory of a room-temperature silicon quantum dot device as a sensitive electrometer
- 2004
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Ingår i: Journal of Applied Physics. - Melville, NY : American Institute of Physics (AIP). - 0021-8979 .- 1089-7550. ; 95:1, s. 323-326
-
Tidskriftsartikel (refereegranskat)abstract
- We consider theoretically the use of a room-temperature silicon quantum dot based device for electrometer applications. The low power device includes two split gates that quantize the electronic energy levels in the emitter and collector regions. The base consists of a silicon quantum dot buried in silicon dioxide. The small size of the dotand quantization of the states in the leads combined to allow the device to operate at room temperature. The nonlinear current-voltage characteristics can be significantly altered by small changes to the potential of the split gates. Power dissipation in the device therefore changes with the split gate voltage, and this can be exploited in electrometerapplications. A simple model of the power dissipated when the device is part of a microwave resonant inductor-resistor-capacitor tank circuit suggests that large changes indevice power can be achieved by changing the gate voltage, thereby forming a measurable signal. We also demonstrate that the power dissipation in the device changes as the base width is varied, and that the current through the device increases exponentially with a decrease in base width. (©2004 American Institute of Physics)
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| 2. |
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| 3. |
- Asad, Muhammad, 1986, et al.
(författare)
-
Enhanced high-frequency performance of top-gated graphene FETs due to substrate-induced improvements in charge carrier saturation velocity
- 2021
-
Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 68:2, s. 899-902
-
Tidskriftsartikel (refereegranskat)abstract
- High-frequency performance of top-gated graphene field-effect transistors (GFETs) depends to a large extent on the saturation velocity of the charge car-riers, a velocity limited by inelastic scattering by surface optical phonons from the dielectrics surrounding the chan-nel. In this work, we show that by simply changing the graphene channel surrounding dielectric with a material having higher optical phonon energy, one could improve the transit frequency and maximum frequency of oscillation of GFETs. We fabricated GFETs on conventional SiO2/Si substrates by adding a thin Al2O3 interfacial buffer layer on top of SiO2/Si substrates, a material with about 30% higher optical phonon energy than that of SiO2, and compared performance with that of GFETs fabricated without adding the interfacial layer. From S-parameter measurements, a transit frequency and a maximum frequency of oscillation of 43 GHz and 46 GHz, respectively, were obtained for GFETs on Al2O3 with 0.5 µm gate length. These values are approximately 30% higher than those for state-of-the-art GFETs of the same gate length on SiO2. For relating the improvement of GFET high-frequency performance to improvements in the charge carrier saturation velocity, we used standard methods to extract the charge carrier veloc-ity from the channel transit time. A comparison between two sets of GFETs with and without the interfacial Al2O3 layer showed that the charge carrier saturation velocity had increased to 2·10^7 cm/s from 1.5·10^7 cm/s.
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| 4. |
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| 5. |
- Asad, Muhammad, 1986, et al.
(författare)
-
The dependence of the high-frequency performance of graphene field-effect transistors on channel transport properties
- 2020
-
Ingår i: IEEE Journal of the Electron Devices Society. - 2168-6734. ; 8, s. 457-464
-
Tidskriftsartikel (refereegranskat)abstract
- This paper addresses the high-frequency performance limitations of graphene field-effect transistors (GFETs) caused by material imperfections. To understand these limitations, we performed a comprehensive study of the relationship between the quality of graphene and surrounding materials and the high-frequency performance of GFETs fabricated on a silicon chip. We measured the transit frequency (fT) and the maximum frequency of oscillation (fmax) for a set of GFETs across the chip, and as a measure of the material quality, we chose low-field carrier mobility. The low-field mobility varied across the chip from 600 cm2/Vs to 2000 cm2/Vs, while the fT and fmax frequencies varied from 20 GHz to 37 GHz. The relationship between these frequencies and the low-field mobility was observed experimentally and explained using a methodology based on a small-signal equivalent circuit model with parameters extracted from the drain resistance model and the charge-carrier velocity saturation model. Sensitivity analysis clarified the effects of equivalent-circuit parameters on the fT and fmax frequencies. To improve the GFET high-frequency performance, the transconductance was the most critical parameter, which could be improved by increasing the charge-carrier saturation velocity by selecting adjacent dielectric materials with optical phonon energies higher than that of SiO2.
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| 6. |
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| 7. |
- Bao, Jie, et al.
(författare)
-
Synthesis and Applications of Two-Dimensional Hexagonal Boron Nitride in Electronics Manufacturing
- 2016
-
Ingår i: Electronic Materials Letters. - : Springer Science and Business Media LLC. - 1738-8090 .- 2093-6788. ; 12:1, s. 1-16
-
Forskningsöversikt (refereegranskat)abstract
- In similarity to graphene, two-dimensional (2D) hexagonal boron nitride (hBN) has some remarkable properties, such as mechanical robustness and high thermal conductivity. In addition, hBN has superb chemical stability and it is electrically insulating. 2D hBN has been considered a promising material for many applications in electronics, including 2D hBN based substrates, gate dielectrics for graphene transistors and interconnects, and electronic packaging insulators. This paper reviews the synthesis, transfer and fabrication of 2D hBN films, hBN based composites and hBN-based van der Waals heterostructures. In particular, this review focuses on applications in manufacturing electronic devices where the insulating and thermal properties of hBN can potentially be exploited. 2D hBN and related composite systems are emerging as new and industrially important materials, which could address many challenges in future complex electronics devices and systems.
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| 8. |
- Bao, Jie, 1982, et al.
(författare)
-
Two-dimensional hexagonal boron nitride as lateral heat spreader in electrically insulating packaging
- 2016
-
Ingår i: Journal of Physics D: Applied Physics. - : IOP Publishing. - 1361-6463 .- 0022-3727. ; 49:July 2016, s. 265501-
-
Tidskriftsartikel (refereegranskat)abstract
- The need for electrically insulating materials with a high in-plane thermal conductivity for lateral heat spreading applications in electronic devices has intensified studies of layered hexagonal boron nitride (h-BN) films. Due to its physicochemical properties, h-BN can be utilised in power dissipating devices such as an electrically insulating heat spreader material for laterally redistributing the heat from hotspots caused by locally excessive heat flux densities. In this study, two types of boron nitride based heat spreader test structures have been assembled and evaluated for heat dissipation. The test structures separately utilised a few-layer h-BN film with and without graphene enhancement drop coated onto the hotspot test structure. The influence of the h-BN heat spreader films on the temperature distribution across the surface of the hotspot test structure was studied at a range of heat flux densities through the hotspot. It was found that the graphene-enhanced h-BN film reduced the hotspot temperature by about 8–10°C at a 1000 W/cm2 heat flux density, a temperature decrease significantly larger than for h-BN film without graphene enhancement. Finite element simulations of the h-BN film predict that further improvements in heat spreading ability are possible if the thermal contact resistance between the film and test chip are minimised.
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| 9. |
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| 10. |
- Björk, Magnus, 1977, et al.
(författare)
-
Exposed Datapath for Efficient Computing
- 2006
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- We introduce FlexCore, which is the first exemplar of a processor based on the FlexSoC processor paradigm. TheFlexCore utilizes an exposed datapath for increased performance. Microbenchmarks yield a performance boost of a factor of two over a traditional five-stage pipeline with the same functional units as the FlexCore.We describe our approach to compiling for the FlexCore.A flexible interconnect allows the FlexCore datapath to bedynamically reconfigured as a consequence of code generation. Additionally, specialized functional units may be introduced and utilized within the same architecture and compilation framework. The exposed datapath requires a wide control word. The conducted evaluation of two micro benchmarks confirms that this increases the instruction bandwidth and memory footprint. This calls for an efficient instruction decoding as proposed in the FlexSoC paradigm.
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| 11. |
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| 12. |
- Edwards, Michael, 1986, et al.
(författare)
-
Finite element simulation of 2D-based materials as heat spreaders
- 2016
-
Ingår i: IMAPS Nordic Annual Conference 2016 Proceedings. - 9781510827226
-
Konferensbidrag (refereegranskat)abstract
- Since the discovery of graphene, the first discovered 2D material, by Novoselov and Geim in 2004, the field of 2D materials has taken off and about 20 further 2D materials have been found. One of the most promising of these materials for the passive cooling of chips is hBN. HBN has the very unusual combination of being electrically insulating and thermally conductive, which potentially makes it an ideal material for both laterally spreading heat and passivating hotspots on chips. This gives hBN an advantage over graphene, where the chip requires a SiO2 passivation layer to prevent short circuits. To help evaluate the performance of these heat spreading films, a finite element model has been devised to support the experimental work undertaken in various publications. This model has been validated with experimental data and suggests that both graphene-And hBN-based materials have significant potential in lateral heat spreading applications.
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| 13. |
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| 14. |
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| 15. |
- Fu, Yifeng, 1984, et al.
(författare)
-
Thermal Characterization of Low-Dimensional Materials by Resistance Thermometers
- 2019
-
Ingår i: Materials. - : MDPI AG. - 1996-1944. ; 12:11
-
Forskningsöversikt (refereegranskat)abstract
- The design, fabrication, and use of a hotspot-producing and temperature-sensing resistance thermometer for evaluating the thermal properties of low-dimensional materials are described in this paper. The materials that are characterized include one-dimensional (1D) carbon nanotubes, and two-dimensional (2D) graphene and boron nitride films. The excellent thermal performance of these materials shows great potential for cooling electronic devices and systems such as in three-dimensional (3D) integrated chip-stacks, power amplifiers, and light-emitting diodes. The thermometers are designed to be serpentine-shaped platinum resistors serving both as hotspots and temperature sensors. By using these thermometers, the thermal performance of the abovementioned emerging low-dimensional materials was evaluated with high accuracy.
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| 16. |
- Hedenstierna, Nils, 1959, et al.
(författare)
-
A parallel hierarchical design rule checker
- 1992
-
Ingår i: [3rd] European Conference on Design Automation. - 0818626453 ; 1992, s. 142-146
-
Konferensbidrag (refereegranskat)abstract
- The halo algorithm, a novel and efficient algorithm for hierarchical design-rule checking (DRC) has been modified for parallel processing. Like the sequential halo algorithm, the parallel version identifies repeated subcell interactions and checks them only once thereby improving performance substantially. Inverse layout trees are used to handle interacting primitives hierarchically. The algorithm has been implemented on workstations connected by a local area network and on a shared memory multicomputer.
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| 17. |
- Hedenstierna, Nils, 1959, et al.
(författare)
-
Comments on "A module generator for optimized CMOS buffers"
- 1993
-
Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 1937-4151 .- 0278-0070. ; 12:1, s. 180-181
-
Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- For the original article see ibid., vol.9, no.10, p.1028-46 (1990). In the above-titled paper A.J. Al-Khalili et al. claim that the expression derived by the commenters (1987) for the short-circuit energy dissipation per transition for a CMOS inverter while the n-channel transistor is discharging the load capacitor is not correct, and they suggest that some mistakes were made during the integration. The commenters point out that a rederivation showed that their expression is correct, and even if it is given for equal p- and n-channel transistors, it can easily be generalized to arbitrary p- and n-channel transistor sizes.
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| 18. |
- Hedenstierna, Nils, 1959, et al.
(författare)
-
Formal definitions of edge-based geometric design rules
- 1993
-
Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1937-4151 .- 0278-0070. ; 12:1, s. 59-69
-
Tidskriftsartikel (refereegranskat)abstract
- A structured method for geometric design rule definitions is presented in terms of edge-based constraints. Using this approach, intralayer design rules such as width and spacing of single layers, and interlayer design rules such as clearance, margin, extension, and overlap of two different layers can be specified in terms of two high-level design rule macros only. The tedious and complicated task of specifying detailed design rules in the technology file is thereby eliminated and placed by a simple macro rule file giving a much better overview of the design rules. Efficient rule compilers have been developed to expand these macro descriptions of the design rules onto basic checks for Magic and for corner-based design rule checking. As an example, the MOSIS scalable CMOS design rule set can be described in terms of the two design rule macros only. More complicated design rules, such as conditional and conjunctive design rules, are also discussed.
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| 19. |
- Hedenstierna, Nils, 1959, et al.
(författare)
-
New algorithms for increased efficiency in hierarchical design rule checking
- 1987
-
Ingår i: Integration, the VLSI Journal. - : Elsevier BV. - 0167-9260. ; 5:3-4, s. 319-336
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents two new algorithms that make hierarchical geometric design rule checkers more efficient. The first is a method to reduce the number of design rules to be checked when a subcell interact with layout outside the subcell. The second method checks large array of cells (PLA, RAM, ROM, datapaths) in a very efficient way. It could also be used to validate certain types of module generators. These algorithms have been implemented in a program using corner-based rules and an adaptive quad tree as data structure.
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| 20. |
- Hedenstierna, Nils, 1959, et al.
(författare)
-
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits
- 1993
-
Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 1937-4151 .- 0278-0070. ; 12:2, s. 265 - 272
-
Tidskriftsartikel (refereegranskat)abstract
- The halo algorithm, a new and efficient hierarchical algorithm for corner-based design rule checking, is presented. The basic idea is to check each cell in its context by first identifying all elements that interact with the cell, thereby completely eliminating the rechecks of the traditional hierarchical methods. Identical interactions, repeated at several instances of a cell, are identified and checked as one interaction. The concept of the inverse layout tree is introduced to handle the interacting primitives. No restrictions are enforced on the hierarchical structure of the layout, and error messages are placed in the cells where the errors should be corrected. Performance is exemplified using several test-circuits. It is shown that the halo algorithm offers a five to twentyfold speed increase when the hierarchical circuit description is verified instead of a flattened description.
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| 21. |
- Hedenstierna, Nils, 1959, et al.
(författare)
-
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking
- 1989
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Ingår i: 26th Conference on Design Automation. - 0738-100X. - 0897913108 ; 1989:25-29 June 1989, s. 508-512
-
Konferensbidrag (refereegranskat)abstract
- The inverse layout tree concept is used to perform fully hierarchical DRC without any constraints on the use of overlapping or incomplete cells that are completed at higher levels of hierarchy. Hierarchy is preserved and design rule violations are displayed in the cell where they should be corrected. The DRC is corner-based and processes 200-800 corners/second on a VAX 11/750.
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| 22. |
- Hedenstierna, Nils, 1959, et al.
(författare)
-
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking
- 1988
-
Ingår i: IEEE International Conference on Computer-Aided Design ICCAD. - New York, New York, USA : ACM Press. - 0738-100X. - 0897913108 ; 1988, s. 534-537
-
Konferensbidrag (refereegranskat)abstract
- The inverse layout tree concept is used to perform fully hierarchical DRC without any constraints on the use of overlapping or incomplete cells that are completed at higher levels of hierarchy. Hierarchy is preserved and design rule violations are displayed in the cell where they should be corrected. The DRC is corner-based and processes 200-800 corners/second on a VAX 11/750.
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| 23. |
- Huang, Shirong, et al.
(författare)
-
Infrared Emissivity Measurement for Vertically Aligned Multiwall Carbon Nanotubes (CNTs) Based Heat Spreader Applied in High Power Electronics Packaging
- 2016
-
Ingår i: 6th Electronic System-integration Technology Conference (ESTC 2016). - 9781509014026 ; , s. Article no 7764696-
-
Konferensbidrag (refereegranskat)abstract
- Vertically-aligned multiwall carbon nanotubes were deposited on silicon substrate by low pressure chemical vapor deposition (LPCVD), which can be utilized as heat spreaders in high power electronic packaging due to their remarkable thermal conductivity. The infrared emissivity of the vertically aligned multiwall carbon nanotubes was then characterized based on the FLIR SC600 infrared imaging system. The average infrared emissivity of the multiwall carbon nanotubes sample was about 0.92, which agrees well with experimental results reported before. Scanning electron microscopy (SEM) images of the multiwall carbon nanotubes were further analyzed to explain its high emissivity, and the reason can be attributed to the homogeneous sparseness and aligned structure of the vertically aligned multiwall carbon nanotubes
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| 24. |
- Huang, Shirong, et al.
(författare)
-
The Effects of Graphene-Based Films as Heat Spreaders for Thermal Management in Electronic Packaging
- 2016
-
Ingår i: 2016 17th International Conference on Electronic Packaging Technology, ICEPT 2016. - 9781509013968 ; , s. Art no 7583272; Pages 889-892
-
Konferensbidrag (refereegranskat)abstract
- Graphene-based films (GBF) were fabricated using a chemical conversion process including graphene oxide (GO) preparation by use of Hummer’s method, graphene oxide reduction using L-ascorbic acid (LAA), and finally film formation by vacuum filtration. GBF is considered as a candidate material for thermal management, i.e. for removing heat from hotspots in power electronic packaging, due to its high thermal conductivity. In this work, the GBF heat spreading performance in 3D TSV packaging was analysed using finite element methods (FEM) implemented in the COMSOL software. Both size effects and the influence of the thermal conductivity of the GBF heat spreader on the thermal performance of the 3D TSV package were evaluated. Furthermore, the size effects of the thermal conductive adhesive (TCA) underfill between the chip and the printed circuit board (PCB) were analysed. The results obtained are critical for proper design of graphene-based lateral heat spreaders in high power electronic packaging.
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| 25. |
- Hughes, John, 1958, et al.
(författare)
-
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
- 2003
-
Ingår i: Proceedings of 21st Norchip Conference. ; Riga, Latvia, s. 52-55
-
Konferensbidrag (refereegranskat)abstract
- The FlexSoC project aims at developing a designframework that makes it possible to combine the computational speed and energy-efficiency of specialized hardware accelerators with the flexibility of programmable processors. FlexSoC approaches this problem by defining auniform programming interface across the heterogeneousstructure of processing resources. This paper justifies ourapproach and also discusses the central research issueswe will focus on in the areas of VLSI design, computerarchitecture, and programming and verification.
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| 26. |
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| 27. |
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| 28. |
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| 29. |
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| 30. |
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| 31. |
- Ingvarson, Fredrik, 1972, et al.
(författare)
-
Parameter extraction for bipolar transistors
- 1998
-
Ingår i: Microelectronic Engineering. - 0167-9317. ; 40:3-4, s. 187-94
-
Tidskriftsartikel (refereegranskat)abstract
- Different methods of extracting the DC Gummel-Poon bipolar transistor model parameters are reviewed. First the shortcomings of the classical extraction schemes for the intrinsic model are presented together with some improved procedures. Finally the extraction of the series resistances is addressed.
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| 32. |
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| 33. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
3D chip stacking using planarized carbon nanotubes as through-silicon-vias
- 2009
-
Ingår i: Swedish System on Chip Conference.
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Future miniaturization of advanced electronic systems will require 3D chip-to-chip stacking of high performance processor chips. Such systems raise a number of questions concerning power distribution and thermal management issues. Efficient through-silicon-via (TSV) technology and new thermal interface materials will be required for such systems to be successful. Carbon nanotubes (CNT) have been suggested as a candidate material with good mechanical properties, and good thermal and electrical conductivities superior to those of copper TSVs. In this paper we will describe our efforts on producing through-silicon-vias based on carbon nanotube bundles grown from the bottom of 150 m deep silicon vias with 50*50 µm openings. The resistances of such CNT vias have been electrically measured and found to be about 2.0 kΩ, a result very close to previously reported values. However, these values are orders of magnitude too high for practical use and not at all close to values reported from measurements on short carbon nanotubes. New processes are suggested too improve growth of long CNTs.
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| 34. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
A content-addressable memory cell with MNOS transistors
- 1973
-
Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 8:5, s. 338 - 343
-
Tidskriftsartikel (refereegranskat)abstract
- Describes a new associative memory cell in which MNOS transistors are used as storage elements. The memory can perform functions as a read-only memory and at the same time as a read-write memory. The cell can be read as a random-access memory or as a content-addressable memory. As a CAM certain bits can be masked out, i.e., not compared with the stored bits. The comparison can also be controlled from the memory by the stored words. Since the word length or combinations of normal words can be stored in one word of the memory, fewer memory cells are needed than in an ordinary memory. Searches for groups of words (prime implicands) can be performed. Memory cells with an area of 5000-m- have been built to demonstrate the feasibility of the MNOS-CAM.
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| 35. |
- Jeppson, Kjell, 1947
(författare)
-
A learning tool MOSFET model A stepping-stone from the square-law model to BSIM4
- 2013
-
Ingår i: 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, PATMOS 2013. Karlsruhe, Deutschland. SEP 09-11, 2013. - 9781479911707 ; , s. 39-44
-
Konferensbidrag (refereegranskat)abstract
- Students often experience difficulties grasping the gap between simple square-law MOSFET models and advanced BSIM models with a large number of model parameters for modeling the many second-order short-channel effects(SCE). In this paper, a physics-based learning tool MOSFET model is presented with the aim of serving as a stepping-stone between these two models. The model is based on three model parameters in each of the two regions of strong inversion operation. The three-point model parameter extraction scheme is presented to support student learning and hands-on experience. The model is useful both for small-signal parameter calculations in the analog bias region and for calculation of large-signal currents during logic gate transients. Model accuracy is very good, a lot better than first expected, even if geometry variations have not yet been explored.
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| 36. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
A New Master's Program in Integrated Electronic System Design
- 2008
-
Ingår i: European Workshop on Microelectronics Education. ; EWME 2008:Budapest
-
Konferensbidrag (refereegranskat)abstract
- We present the formation of a new Master’s program in Integrated Electronic System Design (IESD). The main ideas behind the program are; 1) Two parallel introductory courses in the first study quarter: One rather practical top-down VHDL-oriented course, and one more theoretical bottom-up silicon-oriented digital VLSI design course. 2) A new broad course focusing on design methodologies from Electronic System Level (ESL) to VLSI, with hands-on emphasis on ASIC backend methodologies. 3) A large project during the first year spring semester in which the knowledge gained during the fall is utilized in design and verification using several complementing technology platforms. 4) Re-use of existing advanced specialist courses (formal methods, computer architecture, and analog VLSI design).
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| 37. |
- Jeppson, Kjell, 1947
(författare)
-
A Parameter Extraction Methodology for Graphene Field-Effect-Transistors
- 2023
-
Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 70:3, s. 1393-1400
-
Tidskriftsartikel (refereegranskat)abstract
- Graphene field-effect transistors have now been around for more than a decade and their transfer characteristics extensively used for device characterization. Model parameters like low-field charge-carrier mobility and device contact/series resistance have often been the main interest. However, not until recently have the methods for device characterization themselves been the focus of research publications. In this paper, I report on a structured methodology for extracting and validating the extracted GFET model parameter values based on the physics of field-effect transistors in general and of graphene field-effect transistors in particular. During the extraction process the GFET resistance is divided into two parts, a constant part, and a gate-voltage-dependent part where the constant part often has been believed to represent the series/contact resistance. However, part of it depends on the channel length and contains first-order information about mobility degradation. Finally, I show that the main influence of the quantum capacitance can be captured by an equivalent oxide thickness replacing the insulator thickness.
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| 38. |
- Jeppson, Kjell, 1947
(författare)
-
A Physical Approach of MNOS LSI Memory Testing
- 1981
-
Ingår i: Physica Scripta. - : IOP Publishing. - 1402-4896 .- 0031-8949. ; 24:2, s. 427-429
-
Tidskriftsartikel (refereegranskat)abstract
- User-oriented retention test programs for MNOS LSI memories with built-in test modes have been developed. Their application is demonstrated on the 4 kbit Word Alterable Read Only Memory (WAROM) ER 3400 in a qualification inspection by Bofors Aerotronics. Of particular interest in this program is the retention time, read disturb and endurance to repeated reprogramming. It is shown that repeated write/erase cycling causes significant deterioration in both retention and readability after 105W/E cycles.
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| 39. |
- Jeppson, Kjell, 1947
(författare)
-
A Student-Oriented Course in Digital VLSI Design
- 2007
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- As part of the European Community Bologna process the 4.5 year national engineering programs are replaced by a 3+2 year Bachelor and Master program. Coordinated with this reformation a shift from lecture-oriented to student-oriented education is carried through. In this paper some of these efforts are reported in the context of an introductory CMOS VLSI Design course. In times of vanishing student interest in engineering education university programs have become open for students with poor qualifications for university studies. Therefore, special emphasis must be paid to practising also very basic skills that we used to take for granted.
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| 40. |
- Jeppson, Kjell, 1947
(författare)
-
A two-step parameter extraction methodology for graphene field-effect transistors
- 2022
-
Ingår i: IEEE International Conference on Microelectronic Test Structures. ; March
-
Konferensbidrag (refereegranskat)abstract
- Accurate device models and parameter extraction methods are of utmost importance for characterizing graphene field-effect transistors and for predicting their performance in circuit applications. For DC characterization, accurate extraction of the transconductance parameter (i.e., low-field mobility) and series resistance is of particular importance. In this paper, methods for extraction of these parameters will be discussed. A first-order mobility degradation model that can be used to separate information about mobility degradation and series resistance for a set of graphene field-effect transistors will also be discussed. Keywords: graphene field-effect transistors, model parameter extraction, charge-carrier mobility, series resistance, mobility
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| 41. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
Att dela online-resurser
- 2004
-
Ingår i: Netlearning 2002. ; Ronneby:Sverige
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Objectives: In this paper we report on the use of the online MIT Weblab system for characterization of semiconductor devices. In particular we will focus on how to improve student learning in the learning situation made available through online remote laboratories. We will discuss the impact of class size and the role of assignment formulation.Method: Students were given open assignments and had to be active from the start, i e already in formulating and planning the measurement task. Examination of the lab assignment in the undergraduate course was performed through group meetings where an examiner directed individual questions to the lab group members who were to respond with the help of a whiteboard. Individual credits were rewarded to the group members according to performance in this oral examination. Results: The overall impression on the use of online laboratories among engineering program students was generally very positive according to questionnaire responses.Conclusion:In essence, online laboratories enables the students to take a more active role in defining the scope of the assignment they can do measurements when they feel ready for them and re-do them when and if need arises.
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| 42. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
CMOS Circuit Speed and Buffer Optimization
- 1987
-
Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 1937-4151 .- 0278-0070. ; 6:2, s. 270 - 281
-
Tidskriftsartikel (refereegranskat)abstract
- An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown to be the sum of the step-response delay and an input dependent delay that may account for as much as 50-100 percent of the total delay. The matching between the ramp input and the characteristic input waveforms is shown to be easily performed for excellent agreement in output response and propagation delay. Even though the short-circuit current is neglected, its influence is shown to be small and may be corrected. As an example, the timing model is used to optimize CMOS output buffers for minimum delay. If the intrinsic output load capacitance is included in the model, the optimum tapering factor is shown to be not e but a value in the range 3-5 depending on process parameters and design style. Also, due to the input dependence of the propagation delay, the last inverter stage in the buffer should have a larger tapering factor than the other stages for minimum delay.
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| 43. |
- Jeppson, Kjell, 1947
(författare)
-
Design and characterization of MIS devices
- 1976
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This work is a part of the research performed at the Research Laboratory of Electronics (Elektronfysik III), concerning [metal-insulator-semiconductor] MIS field-effect devices. It deals with the properties of different memory devices, such as the [metal-nitride-oxide-semiconductor] MNOS and the [floating-gate avalanche-injection metal-oxide-semiconductor] FAMOS memory transistors, where the [metal insulator semiconductor] MIS structure is utilized for information storage. Paper A describes a new associative memory cell in which MNOS transistors are used as storage elements. Paper B describes the Negative Bias Stress of MOS devices at high electric fields with respect to the degradation observed in MNOS memory devices repeatedly operated at high write/erase gate voltages. Paper C deals with the FAMOS memory device and how the information may be unintentionally changed after a large number of read cycles. Paper D is concerned with some critical problems during fabrication of low threshold voltage CMOS circuits for digital watch applications. Paper E shows the influence of a narrow channel width on the threshold voltage in MOS transistors when modulated by the substrate-source voltage.
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| 44. |
- Jeppson, Kjell, 1947
(författare)
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Dynamic Rams - how they developed during the late 1970´s
- 1988
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Ingår i: Elteknik med aktuell elektronik. ; 1972-1988
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- A summary of papers describing how new generations of semiconductor memories were introduced during the 1970´s and 1980´s.
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| 45. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
Exploring prefix-tree adders using excel spreadsheets
- 2013
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Ingår i: 2013 9th IEEE International Conference on Microelectronic Systems Education, MSE 2013. - 9781479901395 ; Austin, Texas 2-3 June 2013, s. 48-51
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Konferensbidrag (refereegranskat)abstract
- A learning environment based on Microsoft Excel spreadsheets is presented allowing for fast and systematic exploration of different implementations of integer adder designs. The spreadsheet properties are exploited to illustrate both layout and timing properties of an adder design. The usefulness of the learning environment is demonstrated by several different examples. We also describe how the spreadsheet representation can aid the designer at the VHDL level.
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| 46. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
Hotspot test structures for evaluating carbon nanotube microfin coolers and graphene-like heat spreaders
- 2016
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Ingår i: 29th IEEE International Conference on Microelectronic Test Structures (ICMTS), Yokohama, Japan, Mar 28-31, 2016. - 1071-9032. ; 2016-May, s. 32-36
-
Konferensbidrag (refereegranskat)abstract
- The design, fabrication, and use of a hotspot-producing and temperature-sensing test structure for evaluating the thermal properties of carbon nanotubes, graphene and boron nitride for cooling of electronic devices in applications like 3D integrated chip-stacks, power amplifiers and light-emitting diodes is described. The test structure is a simple meander-shaped metal resistor serving both as the hotspot and the temperature thermo-meter. By use of this test structure, the influence of emerging materials like those mentioned above on the temperature of the hotspot has been evaluated with good accuracy).
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| 47. |
- Jeppson, Kjell, 1947, et al.
(författare)
-
Implementing Constructive Alignment in a CDIO-oriented Master’s Program in Integrated Electronic System Design
- 2010
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Ingår i: Proceedings of European Workshop on Microelectronics Education. ; , s. 135-140
-
Konferensbidrag (refereegranskat)abstract
- This presentation reports on the design and implementation of a Master’s program in Integrated Electronic System Design at Chalmers University of Technology from the perspectives of CDIO and constructive alignment. CDIO is an innovative educational concept originating from Massachusetts Institute of Technology (MIT) in which engineering fundamentals are stressed in terms of a Conceive, Design, Implement, and Operate process. Constructive alignment is a concept for creating an integrated learning environment where the teaching and learning activities are aligned with the assessment tasks to ensure that the achieved learning outcomes will correspond to the intended learning outcomes. In a process based on these two concepts, we have built a Master´s program that not only offers the basic theoretical background but also gives the student an opportunity to become competent in the skills that industry needs. Program focus is on the engineering process, on the technology platforms, and on the design tools and methodologies needed by the engineer to be able to contribute to the development of complex electronic systems and products while working in an engineering team.
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| 48. |
- Jeppson, Kjell, 1947
(författare)
-
Increasing student examination rate by use of weekly home assignments
- 2008
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Ingår i: European Workshop on Microelectronics Education. ; (EWME 2008)
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Konferensbidrag (refereegranskat)abstract
- A new course outline for an introductory course in digital integrated circuit design is presented. While the old course was lecture-oriented the new course has a focus on student-oriented learning through weekly home assignments and hands-on design laboratories. As a result of the new outline the examination rate increased from 60 to 90%: 45 out of 50 students passed the examination and they did so with good grades.
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| 49. |
- Jeppson, Kjell, 1947
(författare)
-
Influence of the channel width on the threshold voltage modulation in MOSFETs
- 1975
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 1350-911X .- 0013-5194. ; 11:14, s. 297-299
-
Tidskriftsartikel (refereegranskat)abstract
- The threshold voltage of an MOS field-effect transistor is modulated by the source-to-substrate reverse bias. In the letter, the theory for long- and short-channel transistors is extended to include the influence of the channel width. The result is an analytical expression for the threshold voltage as a function of geometry and bias that agrees well with experimental data.
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| 50. |
- Jeppson, Kjell, 1947
(författare)
-
Microelectronics based on Linear Relationships
- 2008
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Ingår i: European Workshop on Microelectronics Education. ; (EWME 2008)
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Konferensbidrag (refereegranskat)abstract
- The new outline of our introductory course on microelectronic devices is presented. The new course has its focus on the MOSFET and aims at providing students with a genuine understanding of the physics behind the current limiting mechanisms. Identification of the assumptions upon which a device model is based is of central interest in the course as is the conclusion that different assumptions result in different models. Validation of models by measurements is also of great importance as is extraction of model parameters. Sometimes student tend to forget that models are just… models.
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