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Sökning: WFRF:(Lemme M. C.)

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1.
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2.
  • Gottlob, H. D. B., et al. (författare)
  • Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
  • 2009
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
  • Tidskriftsartikel (refereegranskat)abstract
    • We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
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3.
  • Fuchs, A., et al. (författare)
  • Nanowire fin field effect transistors via UV-based nanoimprint lithography
  • 2006
  • Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:6, s. 2964-2967
  • Tidskriftsartikel (refereegranskat)abstract
    • A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20 nm (3 sigma). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.
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4.
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5.
  • Pecunia, Vincenzo, et al. (författare)
  • Roadmap on energy harvesting materials
  • 2023
  • Ingår i: Journal of Physics. - : IOP Publishing. - 2515-7639. ; 6:4
  • Tidskriftsartikel (refereegranskat)abstract
    • Ambient energy harvesting has great potential to contribute to sustainable development and address growing environmental challenges. Converting waste energy from energy-intensive processes and systems (e.g. combustion engines and furnaces) is crucial to reducing their environmental impact and achieving net-zero emissions. Compact energy harvesters will also be key to powering the exponentially growing smart devices ecosystem that is part of the Internet of Things, thus enabling futuristic applications that can improve our quality of life (e.g. smart homes, smart cities, smart manufacturing, and smart healthcare). To achieve these goals, innovative materials are needed to efficiently convert ambient energy into electricity through various physical mechanisms, such as the photovoltaic effect, thermoelectricity, piezoelectricity, triboelectricity, and radiofrequency wireless power transfer. By bringing together the perspectives of experts in various types of energy harvesting materials, this Roadmap provides extensive insights into recent advances and present challenges in the field. Additionally, the Roadmap analyses the key performance metrics of these technologies in relation to their ultimate energy conversion limits. Building on these insights, the Roadmap outlines promising directions for future research to fully harness the potential of energy harvesting materials for green energy anytime, anywhere.
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6.
  • Bell, D. C., et al. (författare)
  • Precision cutting and patterning of graphene with helium ions
  • 2009
  • Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 20:45, s. 455301-
  • Tidskriftsartikel (refereegranskat)abstract
    • We report nanoscale patterning of graphene using a helium ion microscope configured for lithography. Helium ion lithography is a direct-write lithography process, comparable to conventional focused ion beam patterning, with no resist or other material contacting the sample surface. In the present application, graphene samples on Si/SiO(2) substrates are cut using helium ions, with computer controlled alignment, patterning, and exposure. Once suitable beam doses are determined, sharp edge profiles and clean etching are obtained, with little evident damage or doping to the sample. This technique provides fast lithography compatible with graphene, with similar to 15 nm feature sizes.
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7.
  • Driussi, F., et al. (författare)
  • Fabrication, characterization and modeling of strained SOI MOSFETs with very large effective mobility
  • 2007
  • Ingår i: ESSDERC 2007. - 9781424411238 ; , s. 315-318
  • Konferensbidrag (refereegranskat)abstract
    • Strained Silicon on insulators (sSOI) wafers with a supercritical thickness of 58 nm were produced using thin strain relaxed SiGe buffer layers, wafer bonding, selective etch back and epitaxial overgrowth. Raman spectroscopy revealed an homogeneous strain of 0.63 +/- 0.03% in the strained Si layer. Long channel n-type SOI-MOSFETs showed very large electron mobilities up to 1200 cm(2)/Vs in the strained Si devices. These values are more than two times larger than those of reference SOI n-MOSFETs. Mobility simulations with state of the art scattering models are then used to interpret the experiments.
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8.
  • Geringer, V., et al. (författare)
  • Intrinsic and extrinsic corrugation of monolayer graphene deposited on SiO(2)
  • 2009
  • Ingår i: Physical Review Letters. - 0031-9007 .- 1079-7114. ; 102:7, s. 076102-
  • Tidskriftsartikel (refereegranskat)abstract
    • Using scanning tunneling microscopy in an ultrahigh vacuum and atomic force microscopy, we investigate the corrugation of graphene flakes deposited by exfoliation on a Si/SiO(2) (300 nm) surface. While the corrugation on SiO(2) is long range with a correlation length of about 25 nm, some of the graphene monolayers exhibit an additional corrugation with a preferential wavelength of about 15 nm. A detailed analysis shows that the long-range corrugation of the substrate is also visible on graphene, but with a reduced amplitude, leading to the conclusion that the graphene is partly freely suspended between hills of the substrate. Thus, the intrinsic rippling observed previously on artificially suspended graphene can exist as well, if graphene is deposited on SiO(2).
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9.
  • Gottlob, H. D. B., et al. (författare)
  • Gd silicate : A high-k dielectric compatible with high temperature annealing
  • 2009
  • Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
  • Tidskriftsartikel (refereegranskat)abstract
    • The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
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10.
  • Mashoff, T., et al. (författare)
  • Bistability and Oscillatory Motion of Natural Nanomembranes Appearing within Monolayer Graphene on Silicon Dioxide
  • 2010
  • Ingår i: Nano letters (Print). - : American Chemical Society (ACS). - 1530-6984 .- 1530-6992. ; 10:2, s. 461-465
  • Tidskriftsartikel (refereegranskat)abstract
    • The truly two-dimensional material graphene is an ideal candidate for nanoelectromechanics due to its large strength and mobility. Here we show that graphene flakes provide natural nanomembranes of diameter down to 3 nm within its intrinsic rippling. The membranes can be lifted either reversibly or hysteretically by the tip of a scanning tunneling microscope. The clamped-membrane model including van-der-Waals and dielectric forces explains the results quantitatively. AC-fields oscillate the membranes, which might lead to a completely novel approach to controlled quantized oscillations or single atom mass detection.
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11.
  • Vaziri, Sam, et al. (författare)
  • Going ballistic : Graphene hot electron transistors
  • 2015
  • Ingår i: Solid State Communications. - : Elsevier. - 0038-1098 .- 1879-2766. ; 224, s. 64-75
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper reviews the experimental and theoretical state of the art in ballistic hot electron transistors that utilize two-dimensional base contacts made from graphene, i.e. graphene base transistors (GBTs). Early performance predictions that indicated potential for THz operation still hold true today, even with improved models that take non-idealities into account. Experimental results clearly demonstrate the basic functionality, with on/off current switching over several orders of magnitude, but further developments are required to exploit the full potential of the GBT device family. In particular, interfaces between graphene and semiconductors or dielectrics are far from perfect and thus limit experimental device integrity, reliability and performance.
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12.
  • Baus, M, et al. (författare)
  • Monolithic Bidirectional Switch (MBS) - A novel MOS-based power device
  • 2005
  • Ingår i: PROCEEDINGS OF ESSDERC 2005. - 0780392035 ; , s. 473-476
  • Konferensbidrag (refereegranskat)abstract
    • A novel MOS-based power device, the Monolithic Bidirectional Switch (MBS), is investigated in this work. An analytical model is used to explain basic device operating principles. A self-aligned fabrication process of lateral MBS devices with Schottky contacts and local oxidation of silicon technique (LOCOS) is described. Experimental results are compared with the analytical model to analyze the influence of device parasitics. Bidirectional switching and an on/off-current ratio of more than 100 is demonstrated for MBS devices for the first time.
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13.
  • Bell, David C., et al. (författare)
  • Precision material modification and patterning with He ions
  • 2009
  • Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:6, s. 2755-2758
  • Tidskriftsartikel (refereegranskat)abstract
    • The authors report on the use of a helium ion microscope as a potential technique for precise nanopatterning. Combined with an automated pattern generation system, they demonstrate controlled etching and patterning of materials, giving precise command over the geometery of the modified nanostructure. After the determination of suitable doses, sharp edge profiles and clean etching of areas in materials were observed. In this article they present examples of patterning on SiO(2) and graphene, which is particularly relevant. This technique could be an avenue for precise material modification for future graphene based device fabrication. The technique has the potential to revolutionize the way that very thin, one-atomic layer materials are modified in a controlled and predictable way.
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14.
  • Benetti, M., et al. (författare)
  • POLYSILICON MESOSCOPIC WIRES COATED BY Pd AS H(2) SENSORS
  • 2009
  • Ingår i: PROCEEDINGS OF THE 13TH ITALIAN CONFERENCE ON SENSORS AND MICROSYSTEMS. - SINGAPORE : WORLD SCIENTIFIC PUBL CO PTE LTD. ; , s. 161-165
  • Konferensbidrag (refereegranskat)abstract
    • In this work a novel monocrystalline silicon nanowires array has been investigated and presented as hydrogen sensor, designed and fabricated by employing high resolution microfabrication techniques and featuring a high surface/volume ratio. The nanowires arrays makes up the channel of a MOS system, palladium-silicon dioxide-silicon. Several devices have been fabricated by using a SOI (Silicon On Insulator) substrate, Source and Drain have been geometrically patterned by optical lithography and Boron p-doped. Electron Beam Litography (EBL) defined the MOS channel made up of a nanowires array of different length and width in different transistors. The pads of Source and Drain have been manufactured with an aluminium film deposition. The Gate has been fabricated with a grown silicon oxide layer (17.4 nm) and Palladium has been used as gate contact. Polarizing and exposing the device to H(2)/N(2) cycles at different concentrations some preliminary measurements have been successfully conducted.
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15.
  • Czernohorsky, M., et al. (författare)
  • Stability of crystalline Gd(2)O(3) thin films on silicon during rapid thermal annealing
  • 2008
  • Ingår i: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 23:3, s. 035010-
  • Tidskriftsartikel (refereegranskat)abstract
    • We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd(2)O(3) layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack ( silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 degrees C anneal.
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16.
  • Echtermeyer, T. J., et al. (författare)
  • Graphene field-effect devices
  • 2007
  • Ingår i: The European Physical Journal Special Topics. - : Springer Science and Business Media LLC. - 1951-6355 .- 1951-6401. ; 148:1, s. 19-26
  • Tidskriftsartikel (refereegranskat)abstract
    • In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices ( FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors ( MOSFETs).
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17.
  • Gottlob, H. D. B., et al. (författare)
  • 0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes
  • 2006
  • Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:10, s. 814-816
  • Tidskriftsartikel (refereegranskat)abstract
    • In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
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18.
  • Gottlob, H. D. B., et al. (författare)
  • CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics
  • 2006
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 979-985
  • Tidskriftsartikel (refereegranskat)abstract
    • Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.
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19.
  • Henschel, W, et al. (författare)
  • Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates
  • 2004
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:5, s. 739-745
  • Tidskriftsartikel (refereegranskat)abstract
    • A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This kind of transistor allows testing the limits of scalability at relaxed process requirements. Transistor gate lengths down to 12 run have been structured by electron beam lithography (EBL) and specific etching processes. The coupling of the upper gate to the inner transistor is carefully investigated.
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20.
  • Heuser, M, et al. (författare)
  • Fabrication of wire-MOSFETs on silicon-on-insulator substrate
  • 2002
  • Ingår i: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 61-2, s. 613-618
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly. (C) 2002 Elsevier Science B.V. All rights reserved.
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21.
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22.
  • Hurley, P.K., et al. (författare)
  • Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/MetalGate Structures on Silicon
  • 2008
  • Ingår i: J. Electrochem. Soc.. ; 155:2, s. G13-G20
  • Tidskriftsartikel (refereegranskat)abstract
    • In this work, we present experimental results examining the energy distribution of the relatively high (>1×10^11 cm−2) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal–insulator–silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H2/N2 annealing following the gate stack formation, reveals a peak density (~2×10^12 cm−2 eV−1 to ~1×10^13 cm−2 eV−1) at 0.83–0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si(100). The characteristic peak in the interface state density (0.83–0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (Pbo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H2/N2) annealing over the temperature range 350–555°C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed.
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23.
  • Illarionov, Y.Yu., et al. (författare)
  • Bias-temperature instability on the back gate of single-layer double-gated graphene field-effect transistors
  • 2016
  • Ingår i: Japanese Journal of Applied Physics. - : Institute of Physics (IOP). - 0021-4922 .- 1347-4065. ; 55:4
  • Tidskriftsartikel (refereegranskat)abstract
    • We study the positive and negative bias-temperature instabilities (PBTI and NBTI) on the back gate of single-layer double-gated graphene fieldeffect transistors (GFETs). By analyzing the resulting degradation at different stress times and oxide fields we show that there is a significant asymmetry between PBTI and NBTI with respect to their dependences on these parameters. Finally, we compare the results obtained on the high-k top gate and SiO2 back gate of the same device and show that SiO2 gate is more stable with respect to BTI.
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24.
  • Illarionov, Yu.Yu., et al. (författare)
  • Hot-carrier degradation in single-layer double-gated graphene field-effect transistors
  • 2015
  • Ingår i: IEEE International Reliability Physics Symposium Proceedings. - : IEEE conference proceedings. - 9781467373623 ; , s. XT21-XT26
  • Konferensbidrag (refereegranskat)abstract
    • We report a first study of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs). Our results show that HCD in GFETs is recoverable, similarly to the bias-temperature instability (BTI). Depending on the top gate bias polarity, the presence of HCD may either accelerate or suppress BTI. Contrary to BTI, which mainly results in a change of the charged trap density in the oxide, HCD also leads to a mobility degradation which strongly correlates with the magnitude of the applied stress.
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25.
  • Illarionov, Yu.Yu., et al. (författare)
  • Impact of hot carrier stress on the defect density and mobility in double-gated graphene field-effect transistors
  • 2015
  • Ingår i: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. - 9781479969111 ; , s. 81-84
  • Konferensbidrag (refereegranskat)abstract
    • We study the impact of hot-carrier degradation (HCD) on the performance of graphene field-effect transistors (GFETs) for different polarities of HC and bias stress. Our results show that the impact of HCD consists in a change of both charged defect density and carrier mobility. At the same time, the mobility degradation agrees with an attractive/repulsive scattering asymmetry and can be understood based on the analysis of the defect density variation.
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26.
  • Lemme, Max C., 1970-, et al. (författare)
  • Complementary metal oxide semiconductor integration of epitaxial Gd(2)O(3)
  • 2009
  • Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:1, s. 258-261
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, epitaxial gadolinium oxide (Gd(2)O(3)) is reviewed as a potential high-K gate dielectric, both "as deposited" by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a "gentle" replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd(2)O(3) gate dielectrics is explored by carefully controlling the annealing conditions.
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27.
  • Lemme, Max C., 1970-, et al. (författare)
  • Etching of Graphene Devices with a Helium Ion Beam
  • 2009
  • Ingår i: ACS Nano. - : American Chemical Society (ACS). - 1936-0851 .- 1936-086X. ; 3:9, s. 2674-2676
  • Tidskriftsartikel (refereegranskat)abstract
    • We report on the etching of graphene devices with a helium ion beam, including in situ electrical measurement during lithography. The etching process can be used to nanostructure and electrically isolate different regions In a graphene device, as demonstrated by etching a channel in a suspended graphene device with etched gaps down to about 10 nm. Graphene devices on silicon dioxide (02) substrates etch with lower He ion doses and are found to have a residual conductivity after etching, which we attribute to contamination by hydrocarbons.
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28.
  • Lemme, Max C., 1970-, et al. (författare)
  • Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate
  • 2003
  • Ingår i: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 67-8, s. 810-817
  • Tidskriftsartikel (refereegranskat)abstract
    • The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate structure on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 urn. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices. (C) 2003 Elsevier Science B.V. All rights reserved.
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29.
  • Lemme, Max C., 1970-, et al. (författare)
  • Mobility in graphene double gate field effect transistors
  • 2008
  • Ingår i: Solid-State Electronics. - : PERGAMON-ELSEVIER SCIENCE LTD. - 0038-1101 .- 1879-2405. ; 52:4, s. 514-518
  • Tidskriftsartikel (refereegranskat)abstract
    • In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top-down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double-gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra-thin body silicon-on-insulator MOSFETs cannot compete with graphene FET values. (c) 2007 Elsevier Ltd. All rights reserved.
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30.
  • Lemme, Max C., 1970-, et al. (författare)
  • Triple-gate metal-oxide-semiconductor field effect transistors fabricated with interference lithography
  • 2004
  • Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 15:4, s. S208-S210
  • Tidskriftsartikel (refereegranskat)abstract
    • In this work, n-type triple-crate metal-oxide-semiconductor field effect transistors (MOSFETs) are presented, where laser interference lithography (LIL) is integrated into a silicon-on-insulator (SOI) CMOS process to provide for the critical definition of the transistor channels. A mix and match process of optical contact lithography and LIL is developed to achieve device relevant structures. The triple-gate MOSFETs are electrically characterized to demonstrate the feasibility of this low cost fabrication process.
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31.
  • Llatser, I., et al. (författare)
  • Characterization of graphene-based nano-antennas in the terahertz band
  • 2012
  • Ingår i: Proceedings of 6th European Conference on Antennas and Propagation, EuCAP 2012. - : IEEE. - 9781457709180 ; , s. 194-198
  • Konferensbidrag (refereegranskat)abstract
    • Graphene-enabled wireless communications constitute a novel paradigm which has been proposed to implement wireless communications at the nanoscale. Indeed, graphene-based nano-antennas just a few micrometers in size have been predicted to radiate electromagnetic waves at the terahertz band. In this work, the performance of a graphene-based nano-patch antenna in transmission and reception is numerically analyzed. The resonance frequency of the nano-antenna is calculated as a function of its length and width, both analytically and by simulation. The influence of a dielectric substrate with a variable size, and the position of the patch with respect to the substrate is also evaluated. Finally, the radiation pattern of a graphene-based nano-patch antenna is compared to that of an equivalent metallic antenna. These results will prove useful for designers of future graphene-based nano-antennas, which will enable wireless communications at the nanoscale.
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32.
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34.
  • Moreno-Garcia, D., et al. (författare)
  • A Resonant Graphene NEMS Vibrometer
  • 2022
  • Ingår i: Small. - : Wiley. - 1613-6810 .- 1613-6829. ; 18:28
  • Tidskriftsartikel (refereegranskat)abstract
    • Measuring vibrations is essential to ensuring building structural safety and machine stability. Predictive maintenance is a central internet of things (IoT) application within the new industrial revolution, where sustainability and performance increase over time are going to be paramount. To reduce the footprint and cost of vibration sensors while improving their performance, new sensor concepts are needed. Here, double-layer graphene membranes are utilized with a suspended silicon proof demonstrating their operation as resonant vibration sensors that show outstanding performance for a given footprint and proof mass. The unveiled sensing effect is based on resonant transduction and has important implications for experimental studies involving thin nano and micro mechanical resonators that are excited by an external shaker. 
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35.
  • Nazarov, A. N., et al. (författare)
  • Charge trapping in ultrathin Gd2O3 high-k dielectric
  • 2007
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:9-10, s. 1968-1971
  • Tidskriftsartikel (refereegranskat)abstract
    • Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 x 10(-20) cm(2). The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 x 10(12) eV(-1) cm(-2) near the valence band edge.
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36.
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37.
  • Schwarz, Mike, et al. (författare)
  • The Schottky barrier transistor in emerging electronic devices
  • 2023
  • Ingår i: Nanotechnology. - 1361-6528 .- 0957-4484. ; 34:35
  • Forskningsöversikt (refereegranskat)abstract
    • This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable field-effect transistors (FETs) for sensors, neuromorphic hardware and security applications. Similarly, judicious use of an SB can be an asset for applications involving Josephson junction FETs.
  •  
38.
  • Smith, Anderson David, et al. (författare)
  • Graphene-based piezoresistive pressure sensing for uniaxial and biaxial strains
  • 2014
  • Ingår i: 2014 Silicon Nanoelectronics Workshop, SNW 2014. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479956777
  • Konferensbidrag (refereegranskat)abstract
    • The piezoresistive effect in graphene has been experimentally demonstrated for both uniaxial and biaxial strains. For uniaxial strain, rectangular membranes were measured while circular membranes provided biaxial strain. Gauge factors have also been extracted and compared to previous literature as well as simulations.
  •  
39.
  • Wahlbrink, T., et al. (författare)
  • Supercritical drying process for high aspect-ratio HSQ nano-structures
  • 2006
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1124-1127
  • Tidskriftsartikel (refereegranskat)abstract
    • Supercritical resist drying allows the fabrication of high aspect-ratio (AR) resist patterns. The potential of this drying technique to increase the maximum achievable AR and the resolution of the overall lithographic process is analyzed for hydrogen silsesquioxane (HSQ). The maximum achievable AR is doubled compared to conventional nitrogen blow drying. Furthermore, the resolution is improved significantly.
  •  
40.
  • Abermann, S., et al. (författare)
  • Processing and evaluation of metal gate/high-k/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-k dielectric
  • 2007
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638
  • Tidskriftsartikel (refereegranskat)abstract
    • We evaluate various metal gate/high-k/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
  •  
41.
  • Balestra, F., et al. (författare)
  • NANOSIL network of excellence-silicon-based nanostructures and nanodevices for long-term nanoelectronics applications
  • 2008
  • Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 11:5-6, s. 148-159
  • Tidskriftsartikel (refereegranskat)abstract
    • NANOSIL Network of Excellence [NANOSIL NoE web site < www.nanosil-noe.eu >], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed-with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades.
  •  
42.
  • Baus, M., et al. (författare)
  • Device architectures based on graphene channels
  • 2008
  • Ingår i: 2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS. - NEW YORK : IEEE. ; , s. 269-272
  • Konferensbidrag (refereegranskat)abstract
    • Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
  •  
43.
  • Baus, M, et al. (författare)
  • Fabrication of monolithic bidirectional switch devices
  • 2004
  • Ingår i: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73-4, s. 463-467
  • Tidskriftsartikel (refereegranskat)abstract
    • The fabrication scheme of a novel MOS-based power device, a monolithic bidirectional switch (MBS), is presented. This concept allows the integration of a bidirectional switch with the advantages of low power consumption, small package size, and low fabrication costs. Furthermore, device simulations predict a performance benefit for power applications such as matrix converters. In an MBS, the field effect is used to control carrier concentrations in elevated structures made up of nearly intrinsic silicon. A CMOS-compatible nano-fabrication process for the MBS is proposed, employing local oxidation of silicon for self-aligned contact formation. First electrical results are presented. (C) 2004 Elsevier B.V. All rights reserved.
  •  
44.
  • Baus, M., et al. (författare)
  • Fabrication of monolithic bidirectional switch (MBS) devices with MOS-controlled emitter structures
  • 2006
  • Ingår i: PROCEEDINGS OF THE 18TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES &amp; ICS. ; , s. 181-184
  • Konferensbidrag (refereegranskat)abstract
    • A novel high-voltage power device, the Monolithic Bidirectional Switch (MBS) is investigated in this work. Planar MBS devices have been fabricated by a self-aligned fabrication process using local oxidation of silicon technique and self-aligned sificidation. Results obtained from electrical characterization are compared with numerical simulations. Using highly transparent universal contacts, bidirectional switching with an excellent on/off current ratio is demonstrated. On-current densities of 75 A/cm(2) at V(on) = 3 V have been achieved even in an exploratory device structure. Simulations further demonstrate the high potential of the MBS for future power electronic systems such as the matrix converter.
  •  
45.
  • Echtermeyer, T., et al. (författare)
  • Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes
  • 2007
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 617-621
  • Tidskriftsartikel (refereegranskat)abstract
    • Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.
  •  
46.
  • Engström, Olof, 1943, et al. (författare)
  • A generalised methodology for oxide leakage current metric
  • 2008
  • Ingår i: Proceeding of 9th European Workshop on Ultimate Integration of Silicon (ULIS), Udine, Italy. - 9781424417308 ; , s. 167-
  • Konferensbidrag (refereegranskat)abstract
    • From calculations of semiconductor interfacecharge, oxide voltage and tunneling currents for MOSsystems with equivalent oxide thickness (EOT) in therange of 1 nm, rules are suggested for making itpossible to compare leakage quality of different oxideswith an accuracy of a factor 2 – 3 if the EOT is known.The standard procedure suggested gives considerablybetter accuracy than the commonly used method todetermine leakage at VFB+1V for n-type and VFB-1V forp-type substrates.
  •  
47.
  • Engström, Olof, 1943, et al. (författare)
  • Gate stacks
  • 2013
  • Ingår i: Nanoscale CMOS: Innovative Materials, Modeling and Characterization. - : Wiley. ; , s. 23 - 67
  • Bokkapitel (övrigt vetenskapligt/konstnärligt)
  •  
48.
  • Engström, Olof, 1943, et al. (författare)
  • Novel high-k/metal gate materials
  • 2007
  • Ingår i: SiNANO Worksshop at ESSDERC 07, Munich.
  • Konferensbidrag (refereegranskat)
  •  
49.
  • Engström, Olof, 1943, et al. (författare)
  • Properties of Metal/High-k Oxide/Graphene Structures
  • 2017
  • Ingår i: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. ; 80:1, s. 157-176
  • Konferensbidrag (refereegranskat)abstract
    • The challenge of interpreting experimental data from capacitance versus voltage (C-V) measurements on metal/high-k oxide/graphene (MOG) structures is discussed. Theoretical expressions for the influence of interface states, bulk oxide traps, measurement frequency, temperature and puddles are derived and compared with experiments. The nature of oxide traps and their impact on C-V data is treated especially from the view of electron-lattice interaction at electron emission and capture and possible performance as border traps, resembling interface states. We find that characterization on detailed physical origins leading to effects on C-V data is a more complicated issue than the corresponding analysis of metal/oxide/semiconductor (MOS) structures.
  •  
50.
  • Gottlob, H. D. B., et al. (författare)
  • Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics
  • 2006
  • Ingår i: ESSDERC 2006. - 9781424403011 ; , s. 150-153
  • Konferensbidrag (refereegranskat)abstract
    • Two process concepts for integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd2O3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.
  •  
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