| 1. |
- Andric, Stefan, et al.
(författare)
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Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
- 2019
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Ingår i: Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics. - : American Vacuum Society. - 2166-2746 .- 2166-2754. ; 37:6
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Tidskriftsartikel (refereegranskat)abstract
- We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.
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| 2. |
- Duan, Shanghong, 1992, et al.
(författare)
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BUILDING AND CHARACTERIZATION OF SYMMETRIC STRUCTURAL BATTERY
- 2022
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Ingår i: ECCM 2022 - Proceedings of the 20th European Conference on Composite Materials: Composites Meet Sustainability. ; 3, s. 1169-1174
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Konferensbidrag (refereegranskat)abstract
- Recently, a structural battery with multifunctional carbon fibre anode has been reported. The energy density of active material is not fully extracted due to the low ionic conductivity inside the battery. To identify the main region that attributes to the low ion transportation, we assemble a symmetric structural battery with one anode layer in the centre sandwiched between two cathode layers. Such a design can also be treated as a combination of two asymmetric batteries with one full thickness cathode layer plus one half thickness anode layer. Thus, the travelled distance of lithium ions is shortened only in the anode part. It is found that the area energy density of the symmetric structural battery is doubled compared to a reference asymmetric battery. Thus, the additional cathode layer activates the double amount of carbon fibres in the anode. A plausible reason is that only the carbon fibres next to the separator is activated in the battery.
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| 3. |
- Haggren, Tuomas, et al.
(författare)
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InP nanowire p-type doping via Zinc indiffusion
- 2016
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Ingår i: Journal of Crystal Growth. - : Elsevier BV. - 0022-0248. ; 451, s. 18-26
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Tidskriftsartikel (refereegranskat)abstract
- We report an alternative pathway for p-type InP nanowire (NW) doping by diffusion of Zn species from the gas phase. The diffusion of Zn was performed in a MOVPE reactor at 350–500 °C for 5–20 min with either H2 environment or additional phosphorus in the atmosphere. In addition, Zn3P2 shells were studied as protective caps during post-diffusion annealing. This post-diffusion annealing was performed to outdiffuse and activate Zn in interstitial locations. The characterization methods included photoluminescence and single NW conductivity and carrier concentration measurements. The acquired carrier concentrations were in the order of >1017 cm−3 for NWs without post-annealing, and up to 1018 cm−3 for NWs annealed with the Zn3P2 shells. The diffused Zn caused redshift to the photoluminescence signal, and the degree of redshift depended on the diffusion process.
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| 4. |
- Lindelöw, Fredrik, et al.
(författare)
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Doping evaluation of InP nanowires for tandem junction solar cells
- 2016
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 27:6
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Tidskriftsartikel (refereegranskat)abstract
- In order to push the development of nanowire-based solar cells further using optimized nanowire diameter and pitch, a doping evaluation of the nanowire geometry is necessary. We report on a doping evaluation of n-type InP nanowires with diameters optimized for light absorption, grown by the use of metal-organic vapor phase epitaxy in particle-assisted growth mode using tetraethyltin (TESn) as the dopant precursor. The charge carrier concentration was evaluated using four-probe resistivity measurements and spatially resolved Hall measurements. In order to reach the highest possible nanowire doping level, we set the TESn molar fraction at a high constant value throughout growth and varied the trimethylindium (TMIn) molar fraction for different runs. Analysis shows that the charge carrier concentration in nanowires grown with the highest TMIn molar fraction (not leading to kinking nanowires) results in a low carrier concentration of approximately 10(16) cm(-3). By decreasing the molar fraction of TMIn, effectively increasing the IV/III ratio, the carrier concentration increases up to a level of about 10(19) cm(-3), where it seems to saturate. Axial carrier concentration gradients along the nanowires are found, which can be correlated to a combination of changes in the nanowire growth rate, measured in situ by optical reflectometry, and polytypism of the nanowires observed in transmission electron microscopy.
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| 5. |
- Lindelöw, Fredrik, et al.
(författare)
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III-V nanowire MOSFETs with novel self-limiting Λ-ridge spacers for RF applications
- 2020
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Ingår i: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 35:6
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Tidskriftsartikel (refereegranskat)abstract
- We present a semi self-aligned processing scheme for III-V nanowire transistors with novel semiconductor spacers in the shape of Λ-ridges, utilising the effect of slow growth rate on {111}B facets. The addition of spacers relaxes the constraint on the perfect alignment of gate to contact areas to enable low overlap capacitances. The spacers give a field-plate effect that also helps reduce off-state and output conductance while increasing breakdown voltage. Microwave compatible devices with L g = 32 nm showing f T = 75 GHz and f max = 100 GHz are realized with the process, demonstrating matched performance to spacer-less devices but with relaxed scaling requirements.
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| 6. |
- Lindelöw, Fredrik
(författare)
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III-V Nanowires for High-Speed Electronics
- 2020. - Series of licentiate and doctoral theses, 1654-790X
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- III-V compound materials have long been used in RF applications in high-electron-mobility-transistors (HEMTs) and bipolar-junction-transistors (BJTs). Now, III-V is also being viewed as a material candidate for replacing silicon in the n-channel in CMOS processes for increased drive currents and reduced power consumption in future nodes. Another alternative to increase the drive current is to use nanowire channels, where the increased electrostatic control can be utilized for scaling the gate length even further. In this thesis, we have characterized III-V nanowires with Hall-measurements to quantify the carrier concentration and optimize growth parameters. We have fabricated nanowire transistors for both digital and analog applications. Digital transistors made of a single nanowire show state-of-the art performance with low subthreshold slope and simultaneously high transconductance and high on-current. For RF applications, the nanowire technology faces several challenges, mainly due to its inherent higher parasitic capacitance since the filling factor is less than 1. To adapt the DC processing scheme to RF measurements, we have implemented T-gates, two-finger devices, 100 nanowires in parallel with tight pitch and we have developed novel spacer schemes with capacitances almost as low as recessed HEMT devices. These schemes consists of for instance modulation doped InP spacers as well as self-aligned air-spacers. To make the RF nanowire MOSFETs even more competitive, the transoncductance of RF devices needs to be optimized to match that of DC devices.
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| 7. |
- Liu, Yen Po, et al.
(författare)
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Low temperature scanning tunneling microscopy and spectroscopy on laterally grown InxGa1-xAs nanowire devices
- 2020
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 117:16
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Tidskriftsartikel (refereegranskat)abstract
- Laterally grown InxGa1-xAs nanowires (NWs) are promising candidates for radio frequency and quantum computing applications, which, however, can require atomic scale surface and interface control. This is challenging to obtain, not least due to ambient air exposure between fabrication steps, which induces surface oxidation. The geometric and electronic surface structures of InxGa1-xAs NWs and contacts, which were grown directly in a planar configuration, exposed to air, and then subsequently cleaned using atomic hydrogen, are studied using low-temperature scanning tunneling microscopy and spectroscopy (STM/S). Atomically flat facets witha root mean square roughness of 0.12 nm and the InGaAs (001) 4 × 2 surface reconstruction areobserved on the top facet of the NWs and the contacts. STS shows a surface bandgap variation of 30 meV from the middle to the end of the NWs, which is attributed to a compositional variation of the In/Ga element concentration. The well-defined facets and small bandgap variations found after area selective growth and atomic hydrogen cleaning are a good starting point for achieving high-quality interfaces during further processing.
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| 8. |
- Zota, Cezar B., et al.
(författare)
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InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v
- 2016
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Ingår i: 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. - 9781509006373
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Konferensbidrag (refereegranskat)abstract
- We report on In0.85Ga0.15As nanowire MOSFETs (NWFETs) with record performance in several key VLSI metrics. These devices exhibit ION = 555 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V), ION = 365 μA/μm (at IOFF = 10 nA/μm and VDD = 0.5 V) and a quality factor Q = gm/SS of 40, all of which are the highest reported for a III-V as well as silicon transistor. Furthermore, a highly scalable, self-Aligned gate-last fabrication process is utilized, with a single nanowire as the channel. The devices use a 45° angle between the nanowire and the contacts, which allows for up to a 1.4 times longer gate length at a given pitch.
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