| 1. |
- Axer, Philip, et al.
(författare)
-
Building Timing Predictable Embedded Systems
- 2012
-
Rapport (övrigt vetenskapligt/konstnärligt)abstract
- A large class of embedded systems is distinguished from general purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of nondeterminism and make guarantees harder to provide. The intention of this paper is to summarize current state-of-the-art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of “predictability”, and present predictability concerns at different abstractions levels in embedded software design. First, we consider timing predictability of processor instruction sets. Thereafter, We consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach based on the synchronous paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally we discuss how to handle predictability at the level of networked embedded systems, where randomly occurring errors must be considered.
|
|
| 2. |
- Chattopadhyay, Sudipta, et al.
(författare)
-
A Unified WCET Analysis Framework for Multicore Platforms
- 2014
-
Ingår i: ACM Transactions on Embedded Computing Systems. - : Association for Computing Machinery (ACM). - 1539-9087 .- 1558-3465. ; 13:124
-
Tidskriftsartikel (refereegranskat)abstract
- With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.
|
|
| 3. |
- Edin Grimheden, Martin, 1971-, et al.
(författare)
-
Guest Editors Introduction: Special Issue on Education for Cyber-Physical Systems
- 2020
-
Ingår i: IEEE design & test. - : Institute of Electrical and Electronics Engineers (IEEE). - 2168-2356 .- 2168-2364. ; 37:6, s. 5-7
-
Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- Cyber-Physical Systems (CPSs) are integrations of physical systems with computations. Their design poses many challenges. For example, CPS design is interdisciplinary by nature, crossing the boundaries of many engineering disciplines. In addition, there is a potential mismatch between the discrete nature of today’s computing systems and typically continuous physical systems, and CPS design has to meet and adhere to many constraints and take many objectives into account. As a result, education for the CPS design is quite challenging. In this context, the special issue on education for CPS aims to provide educators, industrial representatives, and researchers with a view on the needs and share solutions for embedded and CPS education. The special issue addresses questions such as “How can we ensure that students will be able to work in interdisciplinary teams?,” “What skills and capabilities are required by the engineers of tomorrow?,” “How should the corresponding educational programs be formed?,” and “How can effective pedagogic methods be introduced in this domain?”
|
|
| 4. |
- Karlström, Per Axel, 1979-
(författare)
-
NoGAP: Novel Generator of Accelerators and Processors
- 2010
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- ASIPs are needed to handle the future demand of flexible yet highperformance embedded computing. The flexibility of ASIPs makes them preferable over fixed function ASICs. Also, a well designed ASIP, has a power consumption comparable to ASICs. However the cost associated with ASIP design is a limiting factor for a more wide spread adoption. A number of different tools have been proposed, promising to ease this design process. However all of the current state of the art tools limits the designer due to a template based design process. It blocks design freedoms and limits the I/O bandwidth of the template. We have therefore proposed the Novel Generator of Accelerator and Processors (NoGAP). NoGAP is a design automation tool for ASIP andaccelerator design that puts very few limits on what can be designed, yet NoGAP gives support by automating much of the tedious anderror prone tasks associated with ASIP design.This thesis will present NoGAP and much of its key concepts. Such as; the NoGAP-CL) which is a language used to implement processors in NoGAP, This thesis exposes NoGAP's key technologies, which include automatic bus and wire sizing, instruction decoder and pipeline management, how PC-FSMs can be generated, how an assembler can be generated, and how cycle accurate simulators can be generated.We have so far proven NoGAP's strengths in three extensive case studies, in one a floating point pipelined data path was designed, in another a simple RISC processor was designed, and finally one advanced RISC style DSP was designed using NoGAP. All these case studies points to the same conclusion, that NoGAP speeds up development time, clarify complex pipeline architectures, retains design flexibility, and most importantly does not incur much performance penalty, compared to hand optimized RTL code.We belive that the work presented in this thesis shows that NoGAP, using our proposed novel approach to micro architecture design, can have a significant impact on both academic and industrial hardware design. To our best knowledge NoGAP is the first system that has demonstrated that a template free processor construction framework can be developed and generate high performance hardware solutions.
|
|
| 5. |
- Marwedel, Peter, et al.
(författare)
-
Survey on Education for Cyber-Physical Systems
- 2020
-
Ingår i: IEEE design & test. - : Institute of Electrical and Electronics Engineers (IEEE). - 2168-2356 .- 2168-2364. ; 37:6
-
Tidskriftsartikel (refereegranskat)abstract
- Cyber-physical systems (CPSs) have proliferated our daily lives. Hence, it is imperative that we create a workforce ready to take up the challenges offered by this domain. This article presents a survey regarding the educational efforts on CPS design all over the world -Partha Pratim Pande, Washington State University.
|
|
