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| 2. |
- Andersson, Oskar, et al.
(författare)
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Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS
- 2013
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Ingår i: Proceedings of the ESSCIRC (ESSCIRC), 2013. - 1930-8833. - 9781479906437 ; , s. 192-200
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Konferensbidrag (refereegranskat)abstract
- Two standard-cell based memories (SCMs) for op- eration in the subthreshold (sub-VT) region are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual- VT approach to balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implemen- tation; and 2) a purely MUX-based implementation with the 1st stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65 nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively.
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| 3. |
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| 4. |
- Andersson, Oskar, et al.
(författare)
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Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
- 2013
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub- VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D- latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220mV) and a total energy of 14fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65 nm CMOS reported to date.
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| 5. |
- Andersson, Oskar, et al.
(författare)
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Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
- 2016
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Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 63:6, s. 806-817
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Tidskriftsartikel (refereegranskat)abstract
- In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (Vth) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and channel length stretching results in lowest leakage power. Alternatively, a pass- transistor based latch as storage element reduces the area footprint at a cost of reduced access speed, which can be compensated by using a lower-Vth pass-transistor. However, relatively high speed (tens of MHz) in the near- to subthreshold (sub-Vth) region is achievable if general purpose transistors are used instead of low power transistors. A discussion is included to illustrate when to implement ULV memories using SCMs and when to choose sub-Vth SRAMs. The discussion shows that the border is between 4-6 kb, depending on the number of words and the wordlength configuration.
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| 6. |
- Constantin, Jeremy, et al.
(författare)
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An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
- 2013
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Ingår i: IFIP Advances in Information and Communication Technology. - Berlin, Heidelberg : Springer Berlin Heidelberg. - 9783642450723 - 9783642450730 ; 418, s. 88-106
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Bokkapitel (refereegranskat)abstract
- Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog- and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compression kernel is a vital ingredient to maximize battery lifetime. In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-VT) regime. The design is equipped with specific sub-VT capable standard-cell based memories, to enable low-voltage operation with low leakage. Our results show that the proposed ASIP accomplishes 62× speed-up and 11.6× power savings with respect to a straightforward CS implementation running on the baseline low-power processor without instruction set extensions.
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| 7. |
- Constantin, Jeremy, et al.
(författare)
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TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
- 2012
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Ingår i: IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC), 2012. - 9781467326575 ; , s. 159-164
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Konferensbidrag (refereegranskat)abstract
- Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.
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| 9. |
- Meinerzhagen, Pascal, et al.
(författare)
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Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
- 2011
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - 2156-3365. ; 1:2, s. 173-182
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, standard-cell based memories (SCMs)are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.
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| 10. |
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| 11. |
- Mohammadi, Babak, et al.
(författare)
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A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
- 2014
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Ingår i: [Host publication title missing].
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Konferensbidrag (refereegranskat)abstract
- The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power
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