| 1. |
- Fakih, Maher, et al.
(författare)
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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
- 2019
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Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 9:1
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Tidskriftsartikel (refereegranskat)abstract
- With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
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| 2. |
- Jocevski, Milan, et al.
(författare)
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Harmonized Supervision of Degree Project Work
- 2019
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Konferensbidrag (refereegranskat)abstract
- Background and purposeEffective supervision practices are vital for the educational and professional development of students,for continuous growth of supervisors, as well as for the development of respective scientific fields. In lightof different learning styles (Taylor & Beasley 2005) and having in mind the time resource constraints ofsupervisors, it is not easy to point out the best pedagogical approach to supervision that maximizes thelearning experience. In addition to the traditional individual supervision (IS) style there are other options(e.g., group supervision (GS) and peer supervision (PS)), which offer certain advantages. These threestyles do not exclude each other, but can rather be combined to complement each other’s strengths.In order to maximize the effectiveness of combining multiple approaches, it is essential to understand itsadvantages and disadvantages. Based on a survey of different experiences among supervisors andstudents collected from different Swedish education institutions, our paper suggests ways to optimizethe supervision processes. Moreover, we call it harmonized supervision, and belive that it would savetime and effort for the supervisors, and help students to overcome the individual limitations of eachsupervision style. Work done/work in progressIn order to study the preferences of students and supervisors with respect to IS, GS, and PS weconducted a survey among faculty members as well as former students at four higher educationinstitutions (HEIs), where our goal was to aggregate their experiences and learnings. The sampling wasdone in two-stages. First, we selected the HEIs. Due to convenience and connections to specific departments at given HEIs that the authors had, we then sent e-mail invitations to both students andsupervisors at these HEIs. In the second stage, through a voluntary process, respondents from bothgroups took part in the survey. Questions in the survey were inspired by the previous experiences of theauthors, and traditional supervision approaches of the affiliated institutions. We asked informants abouttheir experiences, and what they believed were advantages and disadvantages of each of theexperienced supervision styles. Finally, data was analyzed using descriptive statistics and qualitativeanalysis of open-ended questions. Basically, we looked into which style was used the most and in whichsituations, as well as compared different answers that spoke in favor and against each style.Results/observations/lessons learnedIt is interesting to note that supervisors and students had similar views with respect to IS, GS, and PS. Interms of IS “lack of different perspective” and “limited flows of new idea/opinions” are among thedrawbacks highlighted by both supervisors and students. Interestingly enough, a solution to these issuesis readily available among the benefits of GS and PS, i.e., “New ideas for solving problems” and“Diverse feedback”. This observation leads us to conclude that combining IS, GS, and PS in aharmonized supervision approach. By harmonized supervision we refer to an approach where GS andPS are used as the basis, and where IS is used only when needed.Take-home messageRegardless of the choice of the supervision method, one can note that a mixture of style is moreeffective depending on the learner’s phase, which can be broken down in two main stages. In theinitial phase, the supervisor exercises a more structural and contractual style. For instance, thesupervisor acts as a teacher explaining the research method and the student performs it on a step-bystep basis. The next stage is the training phase, where the supervisor can give the student moreformative assessment support and feedback to develope student's skills until a certain autonomy qualityis achieved. Lastly, the learner becomes a master of the thesis topic and therefore becomes moreindependent. When considering supervision it is important to think about different levels of intellectualdevelopment and the social component of the learning process. At the second phase, i.e. trainingphase, the supervisor can adopt group or peer supervision. Engaging the students in peer and groupsupervision may be conducive to the creation of a more secure learning environment. However, it isessential to provide a constructive group constellation and complementing instructions for peers tomaximize the learning outcomes in an efficient manner.
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| 3. |
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| 4. |
- Mohammadat, Tage
(författare)
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A Model-of-Design for Computing Systems : A Categorical Approach
- 2023
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Ingår i: IEEE Access. - : Institute of Electrical and Electronics Engineers (IEEE). - 2169-3536. ; 11, s. 116304-116347
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Tidskriftsartikel (refereegranskat)abstract
- This paper introduces the model of design (MoD), a framework that leverages category theory to study the design and development of computer-driven systems, to the academic and engineering communities dealing with computer systems. The model of design aims to offer a minimal framework for modelling the design and development of embedded computation across domains and abstractions, focusing on functional and extra-functional aspects as well as overarching concerns for automaticity, correctness and reuse. This nuanced approach provides insights into the theory and practice of computer systems design.
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| 5. |
- Mohammadat, Tage
(författare)
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A Proposition for Computing System Design Automaticity and Correctness Potential
- 2022
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Konferensbidrag (refereegranskat)abstract
- Reasoning about the correctness and automation of embedded computing system design across different methodologies is challenging due to the absence of a unifying view of the design problems involved. In this paper, our contribution is describing the necessary conditions for the potentiality of a design method to be automated and correctly produce an implementation. We do this by using the model of design (MoD) framework to capture essential design methodology properties.
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| 6. |
- Mohammadat, Tage, et al.
(författare)
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Multivoltage Aware Resistive Open Fault Model
- 2014
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210 .- 1557-9999. ; 22:2, s. 220-231
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Tidskriftsartikel (refereegranskat)abstract
- Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs causing delay failures and reliability-related concerns. The widespread utilization of multiple supply voltages in contemporary VLSI designs and emerging test methods poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the VDD effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observe that the detectable resistance range versus VDD varies with test speed. We consequently propose a voltage-aware model that divides the full range of open resistances into continuous behavioral intervals and three detectability ranges. The presented model is expected to substantially enhance multivoltage test generation and fault distinction.
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| 7. |
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| 8. |
- Mohammadat, Tage, et al.
(författare)
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Resistive Open Faults Detectability Analysis and Implicationsfor Testing Low Power Nanometric ICs
- 2015
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 23:3, s. 580-583
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Tidskriftsartikel (refereegranskat)abstract
- Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that causetiming failures and reliability risks. The nonmonotonic dependence ofROF-induced delay faults on the supply voltage (VDD) poses a concernas to whether single-VDD testing will suffice for low power nanometricdesigns. Our analysis shows multi-VDD tests could be required, dependingon the test speed. This knowledge can be exploited in small delay faulttesting to reduce the chances of test escapes while minimizing cost.
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| 9. |
- Ngo, Kalle, et al.
(författare)
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Towards a Single Event Upset Detector Based on COTS FPGA
- 2017
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Ingår i: Proceedings of the 2017 IEEE Nordic circuits and systems conference (norcas). - : IEEE.
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Konferensbidrag (refereegranskat)abstract
- The Single Event Upset Detector (SEUD) is 3U CubeSat payload experiment that aims to achieve radiation tolerant computing through detection and correction of SEU bit flips on COTS SRAM FPGAs. Our proposed self-healing architecture applies selective TMR, internal configuration memory scrubbing, and partial reconfiguration and intends to demonstrate a cost-effective alternative to Space-grade radiation hardened SRAM FPGAs. This paper presents an overview of the ongoing development of the SEUD architecture and when complete, the SEUD will be tested on board the KTH MIST student CubeSat that is targeting to be launched in late 2020.
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| 10. |
- Riese, Emma, 1992-, et al.
(författare)
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Scholarship of third-cycle education at KTH: How could doctoral education move forward?
- 2021
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Ingår i: KTH SoTL 2021. - Stockholm : KTH.
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Konferensbidrag (refereegranskat)abstract
- Third-cycle education is an important part of higher education at KTH, but has been limited discussed during previous KTHSoTL conferences. Third-cycle education can, however, face a different set of challenges compared to first and second-cycle, and there have for instance been alarming reports concerning the well-being of doctoral students [1]. The COVID-19 pandemic, has also come with an additional set of challenges for doctoral students [2], and balancing the different roles within a doctoral education program has been reported as difficult [3]. The purpose of this workshop is to highlight, reflect on, discuss and find possible solutions to some of the key issues which were identified in the doctoral student survey, that was conducted by the PhD Chapter at KTH in December 2019 [4].The workshop will be structured around the questions:• How should third-cycle education at KTH look like in ten years, 2031?'• What do we need to change to reach that vision?In December 2019, the PhD Chapter (THS) sent out a survey to all doctoral students that had a registered study activity and email address in Ladok [4]. KTH has also recently sent out a survey to all doctoral students that were admitted to their doctoral studies between the years 2012-2016 [5]. In addition, in UKÄ’s recent review of KTH’s quality assurance system, they highlighted that the doctoral students at KTH were not given as good opportunities to influence their education as first-and second-cycle students, but at the same time recognizing that this is something KTH works with [6]. A short summary of the survey results from the PhD Chapter’s report on “Consequences of COVID-19” gave some insights into how the current pandemic influenced KTH’s doctoral students at the beginning of the pandemic [7].Results/observations/lessons learnedThird-cycle education differentiates from first- and second-cycle, and comes with a set of own challenges. Based on the four sources regarding KTH’s doctoral students [4-7], we like to focus on some key topics that have been identified to have room for improvements:• Supervision [4-5] - what characterizes good supervision and how do we achieve that?• Doctoral student influence and evaluations of study programs [4, 6] - how can this be strengthened and unified across KTH?• Well-being and balance between private and working life [4] - what can be done to support the doctoral students to achieve this? For instance, how can the work culture support a good balance?• Study and work environment [4] - what is working well and what can be improved?• Career opportunities and guidance for doctoral students [4-6] - what can be done to strengthen this?• COVID-19 pandemic consequences [7] - what can we learn from this experience and how can we minimize potential damage to doctoral education on short and long term?
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| 11. |
- Rosvall, Kathrin, et al.
(författare)
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Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
- 2018
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Konferensbidrag (refereegranskat)abstract
- System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.
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| 12. |
- Seyyedi, R., et al.
(författare)
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Towards virtual prototyping of synchronous real-time systems on noc-based MPSoCs
- 2017
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Ingår i: 2017 12th IEEE International Symposium on Industrial Embedded Systems, SIES 2017 - Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538631669 ; , s. 99-102
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Konferensbidrag (refereegranskat)abstract
- NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a 2x2 NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work. NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work.
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