| 1. |
|
|
| 2. |
|
|
| 3. |
- Everett, A., et al.
(författare)
-
Annual down-glacier drainage of lakes and water-filled crevasses at Helheim Glacier, southeast Greenland
- 2016
-
Ingår i: Journal of Geophysical Research - Earth Surface. - 2169-9003 .- 2169-9011. ; 121:10, s. 1819-1833
-
Tidskriftsartikel (refereegranskat)abstract
- Supraglacial lake drainage events are common on the Greenland ice sheet. Observations on the west coast typically show an up-glacier progression of drainage as the annual melt extent spreads inland. We use a suite of remote sensing and modeling techniques in order to study a series of lakes and water-filled crevasses within 20 km of the terminus of Helheim Glacier, southeast Greenland. Automatic classification of surface water areas shows a down-glacier progression of drainage, which occurs in the majority of years between 2007 and 2014. We demonstrate that a linear elastic fracture mechanics model can reliably predict the drainage of the uppermost supraglacial lake in the system but cannot explain the pattern of filling and draining observed in areas of surface water downstream. We propose that the water levels in crevasses downstream of the supraglacial lake can be explained by a transient high-pressure wave passing through the subglacial system following the lake drainage. We support this hypothesis with analysis of the subglacial hydrological conditions, which can explain both the position and interannual variation in filling order of these crevasses. Similar behavior has been observed in association with jokulhaups, surging glaciers, and Antarctic subglacial lakes but has not previously been observed on major outlets of the Greenland ice sheet. Our results suggest that the behavior of near-terminus surface water may differ considerably from that of inland supraglacial lakes, with the potential for basal water pressures to influence the presence of surface water in crevasses close to the terminus of tidewater glaciers.
|
|
| 4. |
- Benkner, S., et al.
(författare)
-
Peppher: Performance Portability and Programmability for Heterogeneous Many-Core Architectures
- 2017
-
Ingår i: Programming Multicore and Many-Core Computing Systems. - Hoboken, NJ, USA : John Wiley & Sons, Inc.. - 9781119332015 - 9780470936900 ; , s. 241-260
-
Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- © 2017 by John Wiley & Sons, Inc. All rights reserved. PEPPHER takes a pluralistic and parallelization agnostic approach to programmability and performance portability for heterogeneous many-core architectures. The PEPPHER framework is in principle language independent but focuses on supporting C++ code with PEPPHER-specific annotations as pragmas or external annotations. The framework is open and extensible; the PEPPHER methodology details how new architectures are incorporated. The PEPPHER methodology consists of rules for how to extend the framework for new architectures. This mainly concerns adaptivity and autotuning for algorithm libraries, the necessary hooks and extensions for the run-time system and any supporting algorithms and data structures that this relies on. Offloading is a specific technique for programming heterogeneous platforms that can sometimes be applied with high efficiency. Offload as developed by the PEPPHER partner Codeplay is a particular, nonintrusive C++ extension allowing portable C++ code to support diverse heterogeneous multicore architectures in a single code base.
|
|
| 5. |
- Benkner, S., et al.
(författare)
-
The PEPPHER approach to programmability and performance portability for heterogeneous many-core architectures
- 2012
-
Ingår i: Advances in Parallel Computing. - : IOS Press. - 1879-808X .- 0927-5452. ; 22, s. 361-368, s. 361-368
-
Konferensbidrag (refereegranskat)abstract
- The European FP7 project PEPPHER is addressing programmability and performance portability for current and emerging heterogeneous many-core architectures. As its main idea, the project proposes a multi-level parallel execution model comprised of potentially parallelized components existing in variants suitable for different types of cores, memory configurations, input characteristics, optimization criteria, and couples this with dynamic and static resource and architecture aware scheduling mechanisms. Crucial to PEPPHER is that components can be made performance aware, allowing for more efficient dynamic and static scheduling on the concrete, available resources. The flexibility provided in the software model, combined with a customizable, heterogeneous, memory and topology aware run-time system is key to efficiently exploiting the resources of each concrete hardware configuration. The project takes a holistic approach, relying on existing paradigms, interfaces, and languages for the parallelization of components, and develops a prototype framework, a methodology for extending the framework, and guidelines for constructing performance portable software and systems-including paths to migration of existing software-for heterogeneous many-core processors. This paper gives a high-level project overview, and presents a specific example showing how the PEPPHER component variant model and resource-aware run-time system enable performance portability of a numerical kernel. © 2012 The authors and IOS Press. All rights reserved.
|
|
| 6. |
- Rivas-Gomez, Sergio, et al.
(författare)
-
Exploring the vision processing unit as co-processor for inference
- 2018
-
Ingår i: Proceedings - 2018 IEEE 32nd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2018. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538655559 ; , s. 589-598
-
Konferensbidrag (refereegranskat)abstract
- The success of the exascale supercomputer is largely debated to remain dependent on novel breakthroughs in technology that effectively reduce the power consumption and thermal dissipation requirements. In this work, we consider the integration of co-processors in high-performance computing (HPC) to enable low-power, seamless computation offloading of certain operations. In particular, we explore the so-called Vision Processing Unit (VPU), a highly-parallel vector processor with a power envelope of less than 1W. We evaluate this chip during inference using a pre-trained GoogLeNet convolutional network model and a large image dataset from the ImageNet ILSVRC challenge. Preliminary results indicate that a multi-VPU configuration provides similar performance compared to reference CPU and GPU implementations, while reducing the thermal-design power (TDP) up to 8x in comparison.
|
|
