| 1. |
- Alam, Syed Asad, 1984-
(författare)
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Techniques for Efficient Implementation of FIR and Particle Filtering
- 2016
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- FIR filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to IIR filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation. One technique to reduce the number of multipliers is to use cascaded sub-filters with lower complexity to achieve the desired specification, known as FRM. One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M. This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alternate number systems like the LNS have been used to implement FIR filters, which reduces the multiplications to additions. FIR filters are realized by directly designing them using ILP in the LNS domain in the minimax sense using finite word length constraints. The branch and bound algorithm, a typical algorithm to implement ILP problems, is implemented based on LNS integers and several branching strategies are proposed and evaluated. The filter coefficients thus obtained are compared with the traditional finite word length coefficients obtained in the linear domain. It is shown that LNS FIR filters provide a better approximation error compared to a standard FIR filter for a given coefficient word length.FIR filters also offer an opportunity in complexity reduction by implementing the multipliers using Booth or standard high-radix multiplication. Both of these multiplication schemes generate pre-computed multiples of the multiplicand which are then selected based on the encoded bits of the multiplier. In TDF FIR filters, one input data is multiplied with a number of coefficients and complexity can be reduced by sharing the pre-computation of the multiplies of the input data for all multiplications. Part of this work includes a systematic and unified approach to the design of such computation sharing multipliers and a comparison of the two forms of multiplication. It also gives closed form expressions for the cost of different parts of multiplication and gives an overview of various ways to implement the select unit with respect to the design of multiplexers.Particle filters are used to solve problems that require estimation of a system. Improved resampling schemes for reducing the latency of the resampling stage is proposed which uses a pre-fetch technique to reduce the latency between 50% to 95% dependent on the number of pre-fetches. Generalized division-free architectures and compact memory structures are also proposed that map to different resampling algorithms and also help in reducing the complexity of the multinomial resampling algorithm and reduce the number of memories required by up to 50%.
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| 2. |
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| 3. |
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| 4. |
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| 5. |
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| 6. |
- Carlsson, Jonas, 1972-, et al.
(författare)
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GALS port implementation in FPGA
- 2005
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Ingår i: National Conf. Radio Science RVK,2005.
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Konferensbidrag (refereegranskat)
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| 7. |
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| 8. |
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| 9. |
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| 10. |
- Jalili, Armin, et al.
(författare)
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Calibration of high-resolution flash ADCS based on histogram test methods
- 2010
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Ingår i: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. - : IEEE. - 9781424481552 ; , s. 114-117
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.
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| 11. |
- Johansson, Håkan, et al.
(författare)
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High-speed lattice wave digital filters for interpolation and decimation
- 1996
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Ingår i: Proc. National Conf. on Radio Science and Communication, RVK'96. ; , s. 543-547
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Bit-serial arithmetic is often advantageous both in terms of small chip area and low power consumption. When using bit-serial arithmetic for implementation of recursive digital filters, the maximal sample frequency is inversely proportional to the coefficient word lengths of the filters. For high-speed applications it is therefore essential to find filter structures with short coefficients. One way to do this is to use cascaded low-order filters instead of one high-order filter. Problems arise though when the cascaded filters are to be used for interpolation and decimation, since the straightforward realization increases the workload due to the different sample rates involved. However, we have developed a novel realization technique which keep the workload at a minimum with the additional possibility to use a high sample frequency. A digital filter for both interpolation and decimation, realized using this novel technique applied on two cascaded lattice wave digital filters, has been implemented. The filter can be used for sample rate conversions between 25 and 50 MHz.
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| 12. |
- Kanders, Hans, et al.
(författare)
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A 1 Million-Point FFT on a Single FPGA
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 66:10, s. 3863-3873
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present the first implementation of a 1 million-point fast Fourier transform (FFT) completely integrated on a single field-programmable gate array (FPGA), without the need for external memory or multiple interconnected FPGAs. The proposed architecture is a pipelined single-delay feedback (SDF) FFT. The architecture includes a specifically designed 1 million-point rotator with high accuracy and a thorough study of the word length at the different FFT stages in order to increase the signal-to-quantization-noise ratio (SQNR) and keep the area low. This also results in low power consumption.
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| 13. |
- Melander, Johan, et al.
(författare)
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An FFT processor based on the SIC architecture with asynchronous PE
- 1996
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Ingår i: Proc. IEEE 1996 Midwest Symp. on Circuits and Systems, MWSCAS'96. - 0780336364 ; , s. III-1313-III-1316
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Konferensbidrag (refereegranskat)abstract
- A SIC architecture with asynchronous bit-serial PEs is presented and applied to the Sande-Tukey's FFT. The resulting architecture can easily be modified for higher throughput and/or lower power consumption. Using this architecture a high-performance chip for use in an OFDM transmission system has been designed.
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| 14. |
- Melander, Johan, et al.
(författare)
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Implementation of a bit-serial FFT processor with a hierarchical control structure
- 1995
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Ingår i: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95. ; , s. I-423-I-426
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Konferensbidrag (refereegranskat)abstract
- A 128-point FFT/IFFT processor has been designed and implemented in a standard CMOS process using the TSPC logic style. The processor uses a high performance bit-serial SIC architecture and calculates an FFT in 58 ms. A structured technique to derive a hierarchical control structure from the pseudo-code for the FFT has been used, resulting in a control unit implemented as a set of co-operating bit-serial control processors. The computational requirements are met using only one butterfly-PE and two RAMs.
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| 15. |
- Nilsson, Peter, et al.
(författare)
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A bit-serial CMOS digital IF-filter for mobile radio using an on-chip clock
- 1994
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Ingår i: Mobile Communications Advanced Systems and Components. - Berlin ; New York : Springer-Vlg, cop.. - 3540578560 - 0387578560 ; , s. 510-521
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Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- A chip for digital intermediate frequency filtering is introduced. The filter is intended move most of the analog intermediate frequency filtering to the digital domain in systems like the American mobile radio system (IS-54). It is a wave digital lattice filter realized with bit-serial arithmetic. Furthermore, a technique for local clocks on chip is presented. The method is based on a ring oscillator and a cycle counter which is controlled from outside the chip. A 0.8 micron technology custom test chip has been fabricated and tested.
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| 16. |
- Nilsson, Peter, et al.
(författare)
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A bit-serial CMOS digital IF-filter for mobile radio using an on-chip clock
- 1994
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Ingår i: Mobile communications advanced systems and components / Lecture notes in Computer Science. - Berlin, Heidelberg : Springer Berlin Heidelberg. - 1611-3349 .- 0302-9743. - 3540578560 ; 783, s. 510-521
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Konferensbidrag (refereegranskat)abstract
- A chip for digital intermediate frequency filtering is introduced. The filter is intended move most of the analog intermediate frequency filtering to the digital domain in systems like the American mobile radio system (IS-54). It is a wave digital lattice filter realized with bit-serial arithmetic. Furthermore, a technique for local clocks on chip is presented. The method is based on a ring oscillator and a cycle counter which is controlled from outside the chip. A 0.8 micron technology custom test chip has been fabricated and tested.
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| 17. |
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| 18. |
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| 19. |
- Palmkvist, Kent, et al.
(författare)
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A fast bit-serial lattice wave digital filter
- 1992
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Ingår i: Proc. NUTEK Workshop on Digital Communications. ; , s. 88-92
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper we discuss the implementation of maximally fast fixed-function digital filters. We demonstrate by means of an example that digital filters with sampling frequencies of more than hundred MHz can efficiently be implemented by using bit-serial PEs. The proposed approach lead to maximally fast filters that require little chip area and have low power consumption. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying equivalence transformations to the signal-flow graph.
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| 20. |
- Palmkvist, Kent, et al.
(författare)
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Arithmetic transformations for fast bit-serial VLSI implementations of recursive algorithms
- 1996
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Ingår i: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96. ; , s. 391-394
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Konferensbidrag (refereegranskat)abstract
- A method to increase the throughput of static recursive algorithms is presented. The signal-flow graph is transformed by first minimizing the number of summation points in the computational loops. A second transformation to rewrite the fixed coefficient multiplications as a sum of weighted signals is then followed by a reordering of the summations. It is how a sum of products can be implemented in this way. Sharing of sub-expressions are also discussed. A bit-serial implementation of a third order bireciprocal lattice WDF is used to illustrate the transformations and sharing of sub-expressions.
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| 21. |
- Palmkvist, Kent, et al.
(författare)
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Design and implementation of an interpolator using wave digital filters
- 1993
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Ingår i: Proc. National Conf. on Radio Science, RVK'93. ; , s. 205-208
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- The design and implementation of an interpolator using wave digital filters is presented. The interpolator increases the sample frequency with a factor of 4, from 800 kHz to 3.2 MHz. The design approach yields implementations with low power consumption and small chip area. The excellent stability and sensitivity properties of wave digital filters are retained.
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| 22. |
- Palmkvist, Kent, et al.
(författare)
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Digital IF filter for mobile radio
- 1995
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Ingår i: Proc. Nordic Radio Symposium, NRS'95. ; , s. 271-276
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- A multirate IF filter for mobile radio has been implemented in silicon. The filter consists of a decimation stage followed by a bandpass filter. Both parts use a lattice wave digital structure. The design and implementation are described beginning with the filter specification and proceed through algorithmic design, operations scheduling, and resource allocation and assignment. Every step tries to minimize the amount of resources in the final implementation, thereby reducing power consumption. Finally the architecture is selected and the system is described using synthesizable VHDL in order to arrive at a chip layout using standard-cell technology. This design technique is used to reduce the design work.
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| 23. |
- Palmkvist, Kent, et al.
(författare)
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Implementation of static DSP algorithms using multiplexed PEs
- 1996
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Ingår i: Proc. 3rd IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'96. - 078033650X ; , s. 824-827
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Konferensbidrag (refereegranskat)abstract
- An efficient and flexible ASIC implementation method suited for static DSP algorithms is presented. It is aimed at low power implementations with moderate speed requirements. The method allows for the processing elements to be multiplexed in order to reduce the amount of resources required. A method to find a minimal number of resources and a corresponding architecture from the cyclic scheduling formulation is described. An implementation of a wave digital bandpass filter is used as an example. The low power consumption and high resource utilization is obtained by using the cyclic scheduling formulation that leads to a maximally fast implementation. The excess speed can be converted to low power consumption by reducing the power supply voltage.
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| 24. |
- Palmkvist, Kent, et al.
(författare)
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Scheduling of data-independent recursive algorithms
- 1995
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Ingår i: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95. ; , s. II-855-II-858
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Konferensbidrag (refereegranskat)abstract
- A new scheduling formulation for data independent recursive algorithms is proposed. This formulation is intuitive and finds a static rate optimal schedules. Processing elements may be non-preemptive and non-homogenous. Comparison with some other common scheduling methods to increase throughput is made.
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| 25. |
- Palmkvist, Kent, 1966-
(författare)
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Studies on the Design and Implementation of Digital Filters
- 1999
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this dissertation an efficient approach to design and implement fixed-function, high-speed recursive digital filters is presented. For a recursive algorithm there is an upper bound on the sample frequency of the corresponding implementation. A maximally fast implementation is an implementation with a sample frequency that is equal to this bound. The maximal sample frequency is determined by the ratio between the number of delay elements and the operation latency in the most time-critical recursive loop(s).We show how maximally fast implementations are obtained using a cyclic scheduling formulation that includes several sample periods. This formulation allows a simple isomorphic mapping of the arithmetic operations to a resourceoptimal hardware structure. The presented implementations are based on bit-serial arithmetic, but digit-serial and bit-parallel arithmetic are also feasible.The cyclic scheduling fonnulation can also be used to design shared-memory architectures with processing elements that are multiplexed to execute the operations. Two different wave digital filters are presented that have been implemented using the proposed design approach.We propose several numerically equivalent transformations that may yield algorithms with reduced iteration period bounds. These transformations are used on a lower level of abstraction, i.e., the arithmetic level, but they affect the critical loops of the algorithms. Further, we define several new latency models for the arithmetic operations with different amounts of pipelining and discuss their effect on the maximal sample frequency.A number of digital filters have been implemented to demonstrate that an increase in sample rate often can be achieved by the use of an appropriate logic style, pipelining of the arithmetic operations, and numerically equivalent transformations.An important advantage of this approach is that the excess speed achieved by a maximally fast implementation can be converted into reduced power consumption by operating a CMOS implementation with a reduced power supply voltage.
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| 26. |
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| 27. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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A CAD tool for synthesis of maximally fast lattice wave digital filters
- 1999
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Ingår i: Proc. National Conf. on Radio Science and Communication, RVK'99. ; , s. 456-460
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- A synthesis tool has been developed that implements the scheduling and the hardware mapping of maximally fast, bit-serial lattice wave digital filters. Such implementations are of interest for use in high-speed applications or in low-power applications after supply voltage scaling. The tool generates a synthesizable VHDL hardware netlist from a set of coefficients describing the filter. The VHDL netlist is further mapped to an ASIC using tools from Mentor Graphics. Currently the tool is capable of synthesizing two lattice wave digital filter structures as well as optimizing the structure for cases like the bireciprocal form of the filter.
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| 28. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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A comparison of three lattice wave digital filter implementations
- 1996
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Ingår i: Proc. Int. Conf. on Signal Processing Applications & Technology, ICSPAT'96. ; , s. II-1909-II-1913
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Konferensbidrag (refereegranskat)abstract
- An approach to schedule lattice wave digital filters so that the maximal sample frequency is obtained is presented. In the approach, bit-serial arithmetic and a scheduling method that decouples the sample period from the scheduling period are used. A lower bound on the scheduling period required to arrive at the minimum sample period is given. Different latency models for the arithmetic operations, and their effect on the minimum sample period are discussed. The operation schedule is mapped to a hardware structure using isomorphic mapping. The throughput of the resulting implementations is comparable to corresponding bit-parallel implementations.
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| 29. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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High-speed multiplication in bit-serial digital filters
- 1996
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Ingår i: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96. ; , s. 179-182
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Konferensbidrag (refereegranskat)abstract
- Canonic signed-digit code representation of multiplier coefficients is often used in digital filters to reduce the required amount of hardware resources. Another approach taken in this paper is to use canonic signed-digit coded coefficients to increase the throughput of the multiplier. We show how the suggested approach applies to serial/parallel multipliers with fixed coefficients. A max¬imally fast implementation of a digital filter is further used as an example to demonstrate the use of the multi¬pliers in recursive digital filters. The resulting bit-serial filters yield a throughput comparable to bit-parallel implemen¬tations, while using only a fractional amount of hardware resources. The filters can be used directly in high-speed applications or in low-power applications after supply voltage scaling.
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| 30. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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Implementation of fast bit-serial lattice wave digital filters
- 1994
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Ingår i: Proc. 1994 IEEE Int. Symp. on Circuits and Systems, ISCAS'94. - 078031915X ; , s. II-113-II-116
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Konferensbidrag (refereegranskat)abstract
- In this paper we discuss the design and implementation of fixed-function wave digital lattice filters. We demonstrate by means of an example that a sampling frequency of more than 130 MHz can be achieved by using bit-serial arithmetic. The proposed approach leads to very fast filters with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. (1981) often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higher-order bireciprocal and non-bireciprocal lattice filters as well as other types of filters.
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| 31. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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Implementation of fast DSP algorithms using bit-serial arithmetic
- 1994
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Ingår i: National Conf. on Electronic Design Automation, EDA-meeting'94.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper we discuss the design and implementation of fixed-function, recursive DSP algorithms. We demonstrate by means of a wave digital lattice filter that a sampling frequency of more than 130 MHz can be achieved for a recursive algorithm by using bit-serial arithmetic. The proposed approach leads to very fast recursive algorithms with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higher-order bireciprocal and non-bireciprocal lattice filters as well as other types of DSP algorithms.
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| 32. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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Implementation of narrow-band lattice wave digital filters
- 1998
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Ingår i: Proc. 1998 IEEE Nordic Signal Processing Symp., NORSIG'98. ; , s. 153-156
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Konferensbidrag (refereegranskat)abstract
- Recently, a filter structure for narrow-band filtering based on lattice wave digital filters was introduced. The structure has increased parallelism over the corresponding direct realization. In this paper, hardware implementation of the filter structure is discussed. The suggested approach uses bit-serial processing elements that are scheduled so that a maximally fast implementation is achieved. An example is given where our implementation approach increases the sample frequency by a factor of 4 compared to a direct realization.
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| 33. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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Maximally fast, bit-serial lattice wave digital filters
- 1996
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Ingår i: Proc. IEEE Digital Signal Processing Workshop, DSPWS'96. - 0780336291 ; , s. 207-210
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Konferensbidrag (refereegranskat)abstract
- An approach to schedule lattice wave digital filters so that the maximal sample frequency is obtained is presented. In the approach, bit-serial arithmetic and a scheduling method that decouples the sample period from the scheduling period are used. A lower bound on the scheduling period required to arrive at the minimum sample period is given. Different latency models for the arithmetic operations, and their effect on the minimum sample period are discussed. The operation schedule is mapped to a hardware structure using isomorphic mapping. The throughput of the resulting implementations is comparable to corresponding bit-parallel implementations.
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| 34. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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On implementation of fast, bit-serial loops
- 1996
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Ingår i: Proc. IEEE 39th Midwest Symp. Circuits and Systems, MWSCAS'96. - 0780336364 ; , s. I-190-I-193
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Konferensbidrag (refereegranskat)abstract
- In this paper we show that it is not sufficient to specify the latency of the processing elements without considering the throughput to arrive at a maximally fast implementation of a recursive algorithm. This result is due to the observation that the latency for serial multiplication actually is dependent on the throughput. We demonstrate how higher throughput is obtained for a first-order recursive filter by increasing the latency of the processing elements. Three models for the latency are examined from corresponding implementations of the filter. For one of the models, canonic signed-digit coding of the coefficient is used which results in a significant increase of the throughput of a serial/parallel multiplier.
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| 35. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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Serial squarers and serial/serial multipliers
- 1996
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Ingår i: Proc. National Conf. on Radio Science and Communication, RVK'96. ; , s. 518-522
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Algorithms for full-precision computation of squares and products are derived. The algorithms yield minimum bit-serial latency. We present logic realizations for the algorithms based on shift accumulators. The realizations have been partitioned into regular bit-slices suitable for hardware implementation.
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| 36. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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Sign-extension and quantization in bit-serial digital filters
- 1996
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Ingår i: Proc. 3rd IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'96. ; , s. 394-397
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Konferensbidrag (refereegranskat)abstract
- A method for handling overflow and quantization in recursive digital filters is described. The method merges the sign-extension required for a serial/parallel multiplier with the required truncation in the bit-serial loops. The method works with maximally fast implementations, i.e., implementations for which the minimum sample period is used as sample period. The method is first described using a first-order recursive filter, and then applied to a third-order bireciprocal lattice wave digital filter.
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| 37. |
- Zhuang, Shengxian, et al.
(författare)
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GALS based approach to the implementation of the DWT filter bank
- 2004
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Ingår i: International Conference on Signal Processing,2004. - Beijing : Publishing House of Electronics Industry. ; , s. 567-
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.
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