| 1. |
- Lindstrand, Jonas, et al.
(författare)
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An integrated 3-level fully adjustable PWM class-D audio amplifier in 0.35um CMOS
- 2008
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Ingår i: [Host publication title missing]. - 9781424424924 ; , s. 168-171
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Konferensbidrag (refereegranskat)abstract
- A Class-D audio amplifier utilizing a fully adjustable 3-level Pulse Width Modulation (PWM) is presented. The amplifier is fully integrated in a 0.35um CMOS process, and is powered by a 3.3V power supply. The system includes an internal fully adjustable triangle-wave oscillator, which is used to generate the PWM carrier. Delivering an output power of 300mW is a differential bridge (7.5cm pMOS, 3cm nMOS), driving a 16¿ load. The THD+N of the system is less than 0.2%, and the efficiency at 300mW is 89%.
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| 2. |
- Radjen, Dejan, et al.
(författare)
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A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
- 2012
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979.
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Tidskriftsartikel (refereegranskat)abstract
- The performance of continuous time deltasigma modulators is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback DACs. To mitigate that effect, a dual switched- capacitor-resistor feedback DAC technique is proposed. The architecture has the additional benefit of reducing the typically high switched-capacitor-resistor DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. The feedback technique has been implemented with a third order, 3-bit delta-sigma modulator for a low power radio receiver, in a 65 nm CMOS process, where it occupies an area of 0.17 mm2. It achieves an SNDR of 70 dB over a 125 kHz bandwidth with an oversampling ratio of 16. The power consumption is 380 lW from a 900 mV supply.
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| 3. |
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| 4. |
- Radjen, Dejan, et al.
(författare)
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A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier
- 2014
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 80:3, s. 387-397
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Tidskriftsartikel (refereegranskat)abstract
- We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.
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| 5. |
- Radjen, Dejan, et al.
(författare)
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A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer
- 2015
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 84:3, s. 409-420
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a low voltage continuous-time delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 W from a 800 mV power supply.
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| 6. |
- Radjen, Dejan
(författare)
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Continuous-Time Delta-Sigma Modulators for Ultra-Low-Power Radios
- 2014
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The modern small devices of today require cheap low power radio frequency (RF) transceivers that can provide reliable connectivity at all times. In an RF transceiver, the analog-to-digital converter (ADC) is one of the most important parts and it is also one of the main power consumers. There are several architectures for implementing an ADC, but in the last decade, continuous-time Delta-Sigma modulators (CT DSMs) have become popular due to their potential of achieving low power consumption and the inherent anti-alias filtering. This thesis investigates different implementations of CT DSMs intended for an ultra-low-power (ULP) receiver operating in the 2.45 GHz ISM band. The main focus is on power saving techniques and jitter insensitive solutions. Papers I and II present a CT DSM with dual switched-capacitor-resistor (DSCR) feedback used in the first DAC. This technique has been developed for the purpose of reducing the jitter sensitivity of the CT DSM while keeping the DAC peak current lower than for conventional SCR feedback. A lower peak current translates into more relaxed slew-rate requirements on the first operational amplifier and thereby less power consumption. Papers III and IV present a low power 2nd-order CT DSM with one operational amplifier. The main objective was to reduce the power consumption of the usually more critical analog part while still achieving a 2nd-order noise shaping. The thesis also examines the possibility of using a successive approximation register (SAR) quantizer instead of the commonly used flash quantizer to reduce the power consumption of the digital part as well.
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| 7. |
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| 8. |
- Sjöland, Henrik, et al.
(författare)
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Ultra low power transceivers for wireless sensors and body area networks
- 2014
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Ingår i: 2014 8th International Symposium on Medical Information and Communication Technology (ISMICT). - 2326-828X. - 9781479948567
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Konferensbidrag (refereegranskat)abstract
- A transceiver suitable for devices in wireless body area networks is presented. Stringent requirements are imposed by the high link loss between opposite sides of the body, about 85 dB in the 2.45 GHz ISM band. Despite this, minimum physical size and power consumption are required, and we target a transceiver with 1 mm2 chip area, 1 mW active power consumption, and data rate 250 kbit/s. The receiver is fully integrated., fabricated and measured in 65-nm CMOS, and size and power consumption are carefully considered at all levels of circuit and system design. The modulation is frequency shift keying, chosen because transmitters can be realized with high efficiency and low spurious emissions; a modulation index 2 creates a midchannel spectral notch. A direct-conversion receiver achieves minimum power consumption. A tailored demodulation structure makes the digital baseband compact and low power. The channel decoder has been implemented in both analog and digital domains to find the most power efficient solution. Antenna design and wave propagation are studied via simulations with phantoms. The 2.45 GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme based on a duty-cycled wake-up receiver is designed.
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| 9. |
- Wang, Ji, et al.
(författare)
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A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio
- 2015
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Ingår i: 2014 NORCHIP. - 9781479954421
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Konferensbidrag (refereegranskat)abstract
- A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.
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| 10. |
- Wu, Ying, et al.
(författare)
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A 0.13µm CMOS ΔΣ PLL FM Transmitter
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.
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