| 1. |
- Borgström, Magnus, et al.
(author)
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Precursor evaluation for in situ InP nanowire doping
- 2008
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In: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 19:44
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Journal article (peer-reviewed)abstract
- The use of tetraethyltin (TESn) and dimethylzinc (DMZn) as in situ n- and p-dopant precursors during particle-assisted growth of InP nanowires is reported. Gate voltage dependent transport measurements demonstrate that the nanowires can be predictably synthesized as either n- or p-type. These doped nanowires can be characterized based on their electric field response and we find that n- type doping scales over a range from 10(17) to 10(19) cm(-3) with increasing input TESn dopant molar fraction. On the other hand, the p-type doping using DMZn saturates at low levels, probably related to a strong increase in nanowire growth rate with increasing DMZn molar fractions. By optimizing growth conditions with respect to tapering, axial pn-junctions exhibiting rectifying behavior were fabricated. The pn-junctions can be operated as light emitting diodes.
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| 2. |
- Passlack, M., et al.
(author)
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Core-shell tfet developments and tfet limitations
- 2019
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In: 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. - 9781728109428
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Conference paper (peer-reviewed)abstract
- Tunneling field-effect transistors (TFET) based on a vertical gate-All-Around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current \mathrm{I}-{\mathrm{o}\mathrm{n}} of 6.7\ \mu \mathrm{A} (NW diameter \mathrm{d}= 10.2\ \mathrm{nm}) at \mathrm{V}-{\mathrm{dd}}=0.3\ \mathrm{V} under low power (LP) conditions (\mathrm{I}-{\mathrm{off}}=1 \mathrm{pA}) for an InAs/GaSb CS TFET. This compares to Si nMOSFET \mathrm{I}-{\mathrm{on}} =2.3\ \mu \mathrm{A} at \mathrm{V}-{\mathrm{dd}}=0.55\ \mathrm{V}(\mathrm{d}=6\ \mathrm{nm}). On the experimental side, scaling of vertical CS NWs resulted in smallest dimensions of \mathrm{d}-{\mathrm{c}}= 17 nm (GaSb core) and \mathrm{t}-{\mathrm{sh}}=3 nm (InAs shell) for a total diameter of 23 nm. VGAA CS nFETs demonstrated drive current of up to 40\ \mu \mathrm{A} (\mathrm{V}-{\mathrm{d}}=0.3\ \mathrm{V}) and subthreshold swing \mathrm{SS}=40\mathrm{mV}/\mathrm{dec}(\mathrm{V}-{\mathrm{d}}=10\mathrm{mV}) for NW diameters between 35-50 nm. Although key TFET properties such as current drive and subthermal SS have been demonstrated using a VGAA CS architecture for the first time, experimental results still lag predictions. An intrinsic relationship between band-To band-Tunneling (BTBT) and \mathrm{D}-{\mathrm{it}} related trap assisted tunneling (TAT) was found which imposes challenging \mathrm{D}-{\mathrm{it}} requirements, in particular for LP \mathrm{I}-{\mathrm{off}} specifications. Complexity of fabrication and a material system foreign to CMOS manufacturing further impact prospects of TFET technology.
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| 3. |
- Schleeh, Joel, 1986, et al.
(author)
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Passivation of InGaAs/InAlAs/InP HEMTs using Al2O3 atomic layer deposition
- 2011
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In: Conference Proceedings - International Conference on Indium Phosphide and Related Materials. 2011 Compound Semiconductor Week and 23rd International Conference on Indium Phosphide and Related Materials, CSW/IPRM 2011, Berlin, 22-26 May 2011. - 1092-8669. - 9781457717536
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Conference paper (peer-reviewed)abstract
- InGaAs/InAlAs/InP HEMTs (InP HEMTs) passivated by Al2O3 atomic layer deposition (ALD) demonstrated improved DC performance compared to Si3N4 plasma enhanced chemical vapour deposition (PECVD). DC measurements have been performed on 130 nm gate-length devices before and after passivation. An increase in maximum drain current density of 20% and extrinsic transconductance of 30% were observed after both ALD and PECVD device passivation. In comparison to PECVD passivated InP HEMTs, ALD passivated devices demonstrated a full suppression of a kink in the I-V characteristics associated with surface traps.
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| 4. |
- Vasen, T., et al.
(author)
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InAs nanowire GAA n-MOSFETs with 12-15 nm diameter
- 2016
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In: 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. - 9781509006373 ; 2016-September
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Conference paper (peer-reviewed)abstract
- InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-All-Around (GAA) MOSFETs with d = 12-15 nm are demonstrated. Ion = 314 μA/μm, and Ssat =68 mV/dec was achieved at Vdd = 0.5 V (Ioff = 0.1 μA/μm). Highest gm measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between gm, Ron, and Imin are discussed.
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| 5. |
- Vasen, T., et al.
(author)
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Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
- 2019
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In: Scientific Reports. - : Springer Science and Business Media LLC. - 2045-2322. ; 9:1
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Journal article (peer-reviewed)abstract
- Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.
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