| 1. |
- Batista, Gracieth Cavalcanti, et al.
(författare)
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Machine learning algorithm partially reconfigured on FPGA for an image edge detection system
- 2024
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Ingår i: Journal of Electronic Science and Technology. - : Elsevier BV. - 1674-862X. ; 22:2
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Tidskriftsartikel (refereegranskat)abstract
- Unmanned aerial vehicles (UAVs) have been widely used in military, medical, wireless communications, aerial surveillance, etc. One key topic involving UAVs is pose estimation in autonomous navigation. A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system (GNSS) signal. However, some factors can interfere with the GNSS signal, such as ionospheric scintillation, jamming, or spoofing. One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images. But a high effort is required for image edge extraction. In this paper, a support vector regression (SVR) model is proposed to reduce this computational load and processing time. The dynamic partial reconfiguration (DPR) of part of the SVR datapath is implementated to accelerate the process, reduce the area, and analyze its granularity by increasing the grain size of the reconfigurable region. Results show that the implementation in hardware is 68 times faster than that in software. This architecure with DPR also facilitates the low power consumption of 4 mW, leading to a reduction of 57% than that without DPR. This is also the lowest power consumption in current machine learning hardware implementations. Besides, the circuitry area is 41 times smaller. SVR with Gaussian kernel shows a success rate of 99.18% and minimum square error of 0.0146 for testing with the planning trajectory. This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application, thus contributing to lower power consumption, smaller hardware area, and shorter execution time.
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| 2. |
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Bioblitz i Arkelstorp 16-17 augusti 2019
- 2020
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Samlingsverk (redaktörskap) (övrigt vetenskapligt/konstnärligt)abstract
- Arkelstorpsviken är den nordvästra delen av Oppmannasjön, som ären av Skånes största sjöar. Idén att genomföra en så kallad Bioblitzvid Arkelstorpsviken föddes under ett styrelsemöte i projektet "En viki Sjöriket Skåne" som är ett samarbete mellan Oppmanna Vånga Bygderåd och Högskolan Kristianstad. Projektets främsta syfte är att hitta en lösning på den kraftiga övergödningen i Arkelstorpsviken. Detta är ett ”Leader”-finansierat projekt, vilket innebär att stommen i projektetär lokal förankring. Det fanns röster i byn som kände att man gav området onödigt dåligt rykte genom att ständigt lyfta fram problemen med vattenstatusen i sjön. Under ett styrelsemöte 30 sep 2018 föddes iden att genom en Bioblitz lyfta fram de positiva värdena i och kring sjön. Den naturliga samarbetspartnern för detta projekt var forskningsmiljön MABH (Man & Biosphere Health) vid Högskolan Kristianstad,vars medlemmar tillsammans besitter en mycket bred biologisk kunskap.Med MABH i ryggen var alltså kompetensen säkrad för att genomföra en Bioblitz. Inbjudningar skickades ut till lokala naturorganisationerför att hitta ännu fler experter som kunde hjälpa till med särskilda artgrupper. Samtidigt jobbade man aktivt lokalt med att försöka engagera intresserad allmänhet. Inbjudningar och direktreklam skickades ut till samtliga hushåll med postadress Arkelstorp. I ett försök att synas genom mediebruset anordnades en tävling, som gick ut på att gissa antalet arter (taxa) som hittades under Bioblitzen. Två lokala företag ställde upp och första priset för den vuxna individ som gissade närmstvar en 3-rätters måltid på Bäckaskogs Slott. De yngre tävlande kunde vinna en kanotutflykt med familjen på Ivögården.
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| 3. |
- Edman, Anders, et al.
(författare)
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A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters
- 1998
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Ingår i: 1998 Symposium on VLSI Circuits, 1998. Digest of Technical Papers. - 0780347668 ; , s. 54-55
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Konferensbidrag (refereegranskat)abstract
- This quadrature DDFS calculates sine and cosine values with a tuning resolution below 1 Hz, by only using an 8 word ROM and interpolation. Two internal 8-bit differential D/A converters generate the four-phase analog output signal. A spurious free dynamic range of 50 dB for low frequencies and 30 dB near Nyquist is achieved.
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| 4. |
- Ingelhag, Per, et al.
(författare)
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A 200 MHz CMOS digital radio frequency memory chip with analog output
- 1993
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Ingår i: Proceedings of the IEEE 1993 Custom Integrated Circuits Conference. - 0780308263 ; , s. 16.3.1-16.3.4
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Konferensbidrag (refereegranskat)abstract
- A single-chip architecture which realizes most of the intermediate-frequency (IF) part of a digital radio frequency memory (DRFM) is presented. The implementation in CMOS technology (Lnom = 1 μm), called the DRFMC, allows different modes of operation with 200-MHz clock frequency (400-MHz nominal). The modes are pulsed signal synthesis, delay line, or continuous-wave (CW) synthesis. The DRFMC is programmable via a DMA interface. A digital signal processing unit and a digital-to-analog converter have been included. The output is analog and digital, which supports cascading of several DRFMCs
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| 5. |
- Ji-Ren, Yuan, et al.
(författare)
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A true single-phase-clock dynamic CMOS circuit technique
- 1987
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200 .- 1558-173X. ; 5:22, s. 899-901
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Tidskriftsartikel (refereegranskat)abstract
- The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.
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| 6. |
- Jordao, Rodolfo, et al.
(författare)
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Design space exploration for safe and optimal mapping of avionics functionality on IMA platforms
- 2023
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Ingår i: AIAA/IEEE Digital Avionics Systems Conference. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- Future avionic systems will be increasingly automated. The size and complexity of the avionics functions in these systems will increase likewise. The degree of attainable automation directly depends on the avionics system's computing power and the efficiency of available tools that map the overall functionality onto the target heterogeneous platform architecture. In safety-critical scenarios, these automation tools must also provide safety guarantees that aid or drive the certification processes. In line with this automation goal, We propose a novel design space exploration technique for the mapping functionality on IMA platforms. The design space exploration technique returns mappings of the functionality onto the platform that are safe and increasingly resource-efficient. A safe mapping is one where the functional and extra-functional requirements are met. A resource-efficient mapping is one where fewer processing elements are used to achieve a safe mapping. More importantly, the proposed technique can return computational proof that no safe mapping is likely possible. This proof is key for safety-critical contexts. To demonstrate the suitability of our technique for avionics systems design scenarios, we investigate its use with an industrial avionics case based on the ones from the PANORAMA ITEA3 project. The case study includes two avionics functionalities, one control functionality, and one streaming-like functionality. The platform is hierarchical and heterogeneous, with elements oriented for higher safety and elements oriented for higher performance. The avionics case-study evaluation shows that our novel design space exploration technique's abstractions and assumptions adequately represent avionics design scenarios directly or through a systematic overestimation. The technique is openly available within the design space exploration tool IDeSyDe. Therefore, designers can immediately benefit from the optimality and safety guarantees given by our novel design space exploration technique in their avionics design process.
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| 7. |
- Karlsson (Söderquist), Ingemar
(författare)
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True single phase clock dynamic CMOS circuit technique
- 1988
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Ingår i: IEEE International Symposium on Circuits and Systems, 1988. ; , s. 475-478
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Konferensbidrag (refereegranskat)abstract
- Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3-μm CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew
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| 8. |
- Lindén, Joakim, et al.
(författare)
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Evaluating the Robustness of ML Models to Out-of-Distribution Data Through Similarity Analysis
- 2023
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Ingår i: Commun. Comput. Info. Sci.. - : Springer Science and Business Media Deutschland GmbH. - 9783031429408 ; , s. 348-359, s. 348-359
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Konferensbidrag (refereegranskat)abstract
- In Machine Learning systems, several factors impact the performance of a trained model. The most important ones include model architecture, the amount of training time, the dataset size and diversity. We present a method for analyzing datasets from a use-case scenario perspective, detecting and quantifying out-of-distribution (OOD) data on dataset level. Our main contribution is the novel use of similarity metrics for the evaluation of the robustness of a model by introducing relative Fréchet Inception Distance (FID) and relative Kernel Inception Distance (KID) measures. These relative measures are relative to a baseline in-distribution dataset and are used to estimate how the model will perform on OOD data (i.e. estimate the model accuracy drop). We find a correlation between our proposed relative FID/relative KID measure and the drop in Average Precision (AP) accuracy on unseen data.
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| 9. |
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| 10. |
- Mesgarzadeh, Behzad, et al.
(författare)
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Reliability Challenges in Avionics due to Silicon Aging
- 2012
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Ingår i: 2012 IEEE 15TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS and SYSTEMS (DDECS). - : IEEE. - 9781467311885 - 9781467311861 - 9781467311878 ; , s. 342-347
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Konferensbidrag (refereegranskat)abstract
- Todays aviation systems are strongly dependent on electronics. Avionics (i.e., aviation electronics) should be highly reliable due to the nature of their applications. CMOS technology, which is widely used in the fabrication of integrated circuits, is continuously scaled to achieve higher performance and higher integration density (i.e., the well-known Moores law). This scaling property creates new challenges in reliability of avionics. As an example, the aging process is speeded up resulting in shorter time to wear-out. This paper investigates reliability challenges in design of avionics caused by silicon aging. It is shown that in the circuits and systems designed in modern CMOS technology, aging phenomenon have to be considered as a serious concern.
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| 11. |
- Sander, Ingo, Professor, 1964-, et al.
(författare)
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TOWARDS CORRECT-BY-CONSTRUCTION DESIGN OF SAFETY-CRITICAL EMBEDDED AVIONICS SYSTEMS
- 2022
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Ingår i: 33rd Congress of the International Council of the Aeronautical Sciences, ICAS 2022. - : International Council of the Aeronautical Sciences. ; , s. 1637-1658
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Konferensbidrag (refereegranskat)abstract
- New methodologies are needed for the development of avionics systems to meet today’s software explosion in complexity and related cost due to the increased functionality in the aircraft. Current design flows for software-intensive systems do not have a clear path from the functional specification to the final implementation and cannot provide real-time guarantees. The situation will become even more difficult because, in the future, more and more applications will share the same computation nodes and the network in a distributed hierarchical network-based system. In order to overcome the present situation, a novel methodology for a correct-by-construction design of safety-critical embedded avionics systems has been created and formulated within the Vinnova NFFP7 project CORRECT. Correct-by-construction design is a radical departure from current design practice, with the potential to decrease the verification costs for future systems significantly. The paper presents the underlying foundation of the methodology, its carefully selected ingredients, and discuss available results and existing tool support. The methodology is based on a disciplined system modelling environment grounded on a sound formal foundation, a design space exploration technique, and a clear path to hardware and software synthesis. An industrial case study investigates the potential of the methodology.
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| 12. |
- Sundström, Timmy, 1981-, et al.
(författare)
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Prognostics of electronic systems through power supply current trends
- 2008
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Ingår i: IEEE Internatioanl Conference on Prognostics and Health Management. - Denver, USA : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- As today's avionic systems highly rely on electronic components, the prognostic of electronic systems in the context of avionics has become crucial. This paper presents a prognostic method applicable to electronic components and systems based on the analysis of the power supply current. In this method, the focus is on trends in the measured power supply current of the device under prognostic process. The discussion in this paper reveals that there is a measurable relationship between the supply current and the remaining lifetime of the electronic devices. The presented methodology is supported by circuit simulations performed on a system consisting of reference circuitry. The prognostic method shows great promise due to the ability of being applicable at any prognostic level.
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| 13. |
- Söderquist, Ingemar, 1960-
(författare)
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CMOS circuits for digital RF systems
- 2002
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This thesis describes some high performance CMOS circuits and architectures developed for digital signal processing of Radio Frequency (RF) signals. Experimental results are demonstrated in a generic radar jammer architecture.The goal is to reach high performance RF system designs utilizing the continuous development of standard commercial CMOS processes. This is done using a comprehensive view with focus on three levels, circuits, devices and architectures. Finally these levels are joined in a system on chip (SoC).At circuit level a new clocking strategy, the true single-phase-clock (TSPC) dynamic CMOS circuit technique, was introduced. TSPC is based on a single clock wire, which simplifies the clock distribution and give higher performance compared to earlier two and four wire solutions. Chips has been designed and fabricated to verify TSPC.At device level two chips has been developed, fabricated and verified. First a single chip Digital Radio Frequency Memory (DRFM) with analog output containing digital parts and on chip D/A converter. Then a single chip Direct Digital Frequency Synthesizer (DDFS) with on chip D/A converters for four-phase analog output. Calculated sine and cosine values are based on ROM tables and interpolation. Both devices utilize TSPC to reach high performance and are frequently used in radar jammers, DRFM for storage of radar pulses and DDFS for frequency selection.At architecture level the material covers three areas: Globally Updated Mesochronous Design Style (GUM-design-style), Expandable High Throughput Vector Based Access Memory Architecture, and Event Driven Data Processing Architecture.GUM-design-style reduces the design effort needed in large high performance synchronous digital designs by early functional partitioning and identification of all needed high speed digital signal links between partitions in the system. Each function is then developed individually which reduces its complexity and by that its design effort needed. Global synchronism is obtained after integration by a calibration procedure.Expandable High Throughput Vector Based Access Memory Architecture improves performance in terms of expandability and throughput for vector access compared to standard memories. Each memory chip has two high-speed data ports used only for connections to adjacent chip. One for connection upward, to device accessing information or a memory chip, the other for connection downward to another memory chip. Expandability is based on mentioned cascade coupling of chips and distributed control function. Memory content is accessed given start point and length of a vector, if the vector is stored on several chips then a distributed internal controller handle the internal management between the chips.Finally, Event Driven Data Processing Architecture increases reconfigurable real-time system performance by extension of traditional programmable computing architecture, software and hardware, to express and execute event and time operations. The architecture is demonstrated in a real-time RF processing radar application.All architectures have been used in chip design, and results verified by measurements.
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| 14. |
- Söderquist, Ingemar
(författare)
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Event driven data processing architecture applied to reconfigurable digital RF system
-
Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- This paper describes a data processing architecture where events and time are in focus. This differs from traditional von Neumann and data flow architectures. Also function and performance are closely handled at all levels of description, implementation and execution. New instruction codes are defined and special circuitry is introduced to express and execute event and time operations. This results in reconfigurable software controlled functionality together with real-time performance close to a dedicated VLSI solution. The architecture is demonstrated in a real-time RF processing radar application and its theory, design, implementation, simulation and testing is presented. A prototype chip, complete with 32-kbyte signal memory, 2-kbyte instruction memory, four processing units in parallel and interfaces for digitized RF signals and host computer, is fabricated in 0.35 μm standard CMOS. Time events of signal data on two simultaneous 8 bit links can be controlled with a time resolution of one clock period. Measurements verified conect function and performance above 400 MHz clock frequency at 3.3 Volt supply. Power consumption is 3.6-Watt @320 MHz.
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| 15. |
- Söderquist, Ingemar, 1960-
(författare)
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Expandable high throughput vector based access memory architecture
- 2002
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Ingår i: Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002. - Bologna : University of Bologna. ; , s. 599-602
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Konferensbidrag (refereegranskat)abstract
- New memory architecture with improved performance in term of expandability and throughput was developed. The architecture, primarily developed for vector access based RF-applications and demonstrated in an electronic warfare application, has potential for closely related applications like cash memories and network routers. A prototype chip with a 64-kbit four-port memory on chip and distributed control logic was designed and fabricated in a standard 0.8 µm BiCMOS process (1M transistors). The research design goal was 10 Gbit/s throughput, using 8 bit data streams and 320 MHz operation frequency. Measurements on prototype chip confirmed the design goal to 50% (5 Gbit/s).
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| 16. |
- Söderquist, Ingemar
(författare)
-
Globally updated mesochronous design style
- 2003
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200 .- 1558-173X. ; 38:7, s. 1242-1249
-
Tidskriftsartikel (refereegranskat)abstract
- In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure due to metastability. Synchronous design styles are widely used, easy to grasp and to implement, and also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most Important is the relationship between physical size and maximum, clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous (GUM) design style is to overcome those drawbacks by identifying all global signal links in the system and adding synchronization circuits to these. System level simplicity, inherited from synchronous design and its tool support, is retained. In this paper, the GUM design style is described, analyzed, and demonstrated. Experimental results from a large-scale high-speed system using three 0.8-µm BiCMOS chips are given. The GUM design style is scaleable and suitable for future system-on-chip applications both on and among chips.
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| 17. |
- Söderquist, Ingemar, 1960-
(författare)
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Globally updated mesochronous design style (GUM-design-style)
- 2002
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Ingår i: Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002. - Bologna : University of Bologna. ; , s. 603-606
-
Konferensbidrag (refereegranskat)abstract
- In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure do to metastability. Synchronous design style is widely used, easy to grasp and to implement, also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous design style (GUM-design-style) is to overcome those by identifying and allowing all single and bidirectional high-speed signal links needed, still retaining the simplicity uncomplicated implementation and tool support. In this paper GUM-design-style is described, analysed and demonstrated. Experimental results from a large-scale high-speed system using three 0.8 µm BiCMOS chips are given. GUM-design-style is scaleable and suitable for future System on Chip (SoC) both on and between chips.
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| 18. |
- Törnblom, John, 1984-
(författare)
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Formal Verification of Tree Ensembles in Safety-Critical Applications
- 2020
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In the presence of data and computational resources, machine learning can be used to synthesize software automatically. For example, machines are now capable of learning complicated pattern recognition tasks and sophisticated decision policies, two key capabilities in autonomous cyber-physical systems. Unfortunately, humans find software synthesized by machine learning algorithms difficult to interpret, which currently limits their use in safety-critical applications such as medical diagnosis and avionic systems. In particular, successful deployments of safety-critical systems mandate the execution of rigorous verification activities, which often rely on human insights, e.g., to identify scenarios in which the system shall be tested.A natural pathway towards a viable verification strategy for such systems is to leverage formal verification techniques, which, in the presence of a formal specification, can provide definitive guarantees with little human intervention. However, formal verification suffers from scalability issues with respect to system complexity. In this thesis, we investigate the limits of current formal verification techniques when applied to a class of machine learning models called tree ensembles, and identify model-specific characteristics that can be exploited to improve the performance of verification algorithms when applied specifically to tree ensembles.To this end, we develop two formal verification techniques specifically for tree ensembles, one fast and conservative technique, and one exact but more computationally demanding. We then combine these two techniques into an abstraction-refinement approach, that we implement in a tool called VoTE (Verifier of Tree Ensembles).Using a couple of case studies, we recognize that sets of inputs that lead to the same system behavior can be captured precisely as hyperrectangles, which enables tractable enumeration of input-output mappings when the input dimension is low. Tree ensembles with a high-dimensional input domain, however, seems generally difficult to verify. In some cases though, conservative approximations of input-output mappings can greatly improve performance. This is demonstrated in a digit recognition case study, where we assess the robustness of classifiers when confronted with additive noise.
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