| 1. |
- Ungureanu, George, et al.
(författare)
-
Parallel software design enabling high-speed reliability testing of inkjet printheads
- 2013
-
Ingår i: International Conference on Digital Printing Technologies. - 9780892083060 ; , s. 60-65
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Konferensbidrag (refereegranskat)abstract
- With new functional applications emerging in the digital printing industry, the need for quantitative knowledge of the reliability of drop-on-demand inkjet printheads increases. Continuous ink circulation using TF Technology™and the resulting channel self-recovery is one of the technologies which decrease the down-time of a single nozzle, but in turn increase the difficulty of an accurate reliability test. Current measuring techniques, namely the a-posteriori verification of printouts on paper proved to be inappropriate. This paper proposes a novel software approach, exploiting signal processing techniques, strong control loops and powerful system design methodologies in order to allow for the correct detection of single missing droplets at run-time. This new system is meant to relieve the effects of the indefinite environment and sources of human error. Preliminary results and the proof-ofconcept demonstrates both the system's and the design method's versatility and potential.
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| 2. |
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| 3. |
- Attarzadeh-Niaki, S. -H, et al.
(författare)
-
A composable and predictable MPSoC design flow for multiple real-time applications
- 2016
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Ingår i: Model-Implementation Fidelity in Cyber Physical System Design. - Cham : Springer International Publishing. ; , s. 157-174
-
Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- Design of real-time MPSoC systems including multiple applications is challenging because temporal requirements of each application must be respected throughout the entire design flow. Currently the design of different applications is often interdependent, making converge to a solution for each application difficult. This chapter proposes a compositional method to design applications independently, and then to execute them without interference. We define a formal modeling framework as a suitable entry point for application design. The models are executable, which enables early detection of specification errors, and include the formal properties of the applications based on well-defined models of computation. We combine this with a predictable MPSoC platform template that has a supporting design flow but lacks a simulation front-end. The structure and behavior of the application models are exported to an intermediate format via introspection which is iteratively transformed for the backend flow. We identify the problems arising in this transformation and provide appropriate solutions. The design flow is demonstrated by a system consisting of two streaming applications where less than half of the design time is dedicated to operating on the integrated system model.
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| 4. |
- Attarzadeh-Niaki, Seyed-Hosein, 1984-, et al.
(författare)
-
A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications
- 2015
-
Konferensbidrag (refereegranskat)abstract
- Design of real-time MPSoC systems including multiple appli-cations is challenging because temporal requirements of each applicationmust be respected throughout the entire design flow. Currently the de-sign of different applications is often interdependent, making converge toa solution for each application difficult. This paper proposes a composi-tional method to design applications independently, and then to executethem without interference. We define a formal modeling framework as asuitable entry point for application design. The models are executable,which enables early detection of specification errors, and include the for-mal properties of the applications based on well-defined models of com-putation. We combine this with a predictable MPSoC platform templatethat has a supporting design flow but lacks a simulation front-end. Thestructure and behavior of the application models are exported to an in-termediate format via introspection which is iteratively adapted for thebackend flow. We identify the problems arising in this adaptation andprovide appropriate solutions. The design flow is demonstrated by a sys-tem consisting of two streaming applications where less than half of thedesign time is dedicated to operating on the integrated system model.
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| 5. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(författare)
-
A Framework for Characterizing Predictable Platform Templates
- 2014
-
Rapport (övrigt vetenskapligt/konstnärligt)abstract
- The design of real-time multiprocessor systems is a very costly and time-consuming process due to the need for extensive verification efforts. Genericcorrect-by-construction system-level design flows, targeting predictable plat-forms, would help to tackle this problem. Unfortunately, because system-level design problems are formulated monolithically, existing methods areeither not powerful enough to perform efficient design space exploration,over-customized to a specific class of platforms, or do not allow to be ex-tended with new heuristics and solving methods, which makes their reusedifficult. We present a formal framework to explicitly capture and character-ize predictable platform templates that can be used to formulate a genericdesign flow for real-time streaming applications in a composable manner. Aproof-of-concept implementation of such a flow is performed and used to mapa JPEG encoder application onto an FPGA-based time-predictable platform.
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| 6. |
- Attarzadeh-Niaki, S. -H, et al.
(författare)
-
An automated parallel simulation flow for cyber-physical system design
- 2021
-
Ingår i: Integration. - : Elsevier BV. - 0167-9260 .- 1872-7522. ; 77, s. 48-58
-
Tidskriftsartikel (refereegranskat)abstract
- Parallel and distributed simulation (PDS) is often employed to tackle the computational intensity of system-level simulation of real-world complex embedded and cyber-physical systems (CPSs). However, CPS models comprise heterogeneous components with diverge semantics for which incompatible PDS approaches are developed. We propose an automated PDS flow based on a formal modeling framework—with necessary extensions—targeting heterogeneous embedded and CPS design. The proposed flow characterizes the sequential executable specification of a heterogeneous model and generates a PDS cluster. State-of-the-art graph partitioning methods are adopted and a new extensible constraint-base formulation of the model partitioning problem is developed. The applicability, effectiveness, and scalability of the proposed flow is demonstrated using case studies.
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| 7. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(författare)
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An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems
- 2013
-
Ingår i: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. - 9781467350716 ; , s. 27-30
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Konferensbidrag (refereegranskat)abstract
- Simulation of complex embedded and cyber-physical systems requires exploitation of the computation power ofavailable parallel architectures. Current simulation environments either do not address this parallelism or use separate models for parallel simulation and for analysis and synthesis, which might lead to model mismatches. We extend a formal modeling framework targeting heterogeneous systems with elements that enable parallel simulations. An automated flow is then proposed that starting from a serial executable specification generates an efficient MPI-based parallel simulation model by using aconstraint-based method. The proposed flow generates parallel models with acceptable speedups for a representative example.
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| 8. |
- Attarzadeh-Niaki, Seyed-Hosein, 1984-, et al.
(författare)
-
An extensible modeling methodology for embedded and CPS design
-
Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- Abstract models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements on modeling and design methodologies. This article argues that the ForSyDe methodology with the necessary extensions can fulfill these requirements and thus qualifies for the design of tomorrow’s systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with precise semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of the commonly used imperative languages and an open-source realization on top of the IEEE standard language SystemC is reported. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features are demonstrated in practice and compared to similar approaches using two relevant case studies.
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| 9. |
- Attarzadeh-Niaki, Seyed-Hosein, 1984-, et al.
(författare)
-
An extensible modeling methodology for embedded and cyber-physical system design
- 2016
-
Ingår i: Simulation (San Diego, Calif.). - : Sage Publications. - 0037-5497 .- 1741-3133. ; 92:8, s. 771-794
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Tidskriftsartikel (refereegranskat)abstract
- models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled, and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements of modeling and design methodologies. This article argues that the Formal System Design (ForSyDe) methodology with the necessary presented extensions fulfills these requirements, and thus qualifies for the design of tomorrow's systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with formal semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of commonly used imperative languages, and an open-source realization on top of the IEEE standard language SystemC is presented. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and by providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features is demonstrated in practice, and compared with similar approaches using a running example and two relevant case studies.
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| 10. |
- Attarzadeh-Niaki, Seyed-Hosein, 1984-, et al.
(författare)
-
Automatic Construction of Models for Analytic Design Space Exploration Problems
-
Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- Due to the variety of application semantics and also the target platforms used in embedded electronic system design, it is challenging to propose a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework to capture the system functionality, a flexible target platform, and a binding policy explicitly using coherent constraint-based representations; together with a method for automatic construction of DSE problem models from them. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from various combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. The constructed models can be solved using different solvers and heuristics.
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| 11. |
- Attarzadeh-Niaki, S. -H, et al.
(författare)
-
Automatic construction of models for analytic system-level design space exploration problems
- 2017
-
Ingår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9783981537093 ; , s. 670-673
-
Konferensbidrag (refereegranskat)abstract
- Due to the variety of application models and also the target platforms used in embedded electronic system design, it is challenging to formulate a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework for automatic construction of system-level DSE problem models based on a coherent, constraint-based representation of system functionality, flexible target platforms, and binding policies. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from different combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. Another potential advantage of this approach is that constructed models can be solved using a variety of standard and ad-hoc solvers and search heuristics.
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| 12. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(författare)
-
Automatic Generation of Virtual Prototypes from Platform Templates
- 2015
-
Ingår i: Languages, Design Methods, and Tools for Electronic System Design. - Switzerland : Springer. - 9783319063164 - 9783319063171 ; , s. 147-166
-
Bokkapitel (refereegranskat)abstract
- Virtual Prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM-2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.
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| 13. |
- Attarzadeh Niaki, Seyed Hosein, et al.
(författare)
-
Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework
- 2011
-
Ingår i: 2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES). - : IEEE Press. - 9781612848181 ; , s. 238-247
-
Konferensbidrag (refereegranskat)abstract
- New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code and IP models in order to be accepted in the industry. To tackle this problem, we introduce the concept of wrappers in the context of a formal heterogeneous embedded system modeling framework. The formalism is based on the language-independent concept of models of computation. Wrappers enable the framework to co-simulate/co-execute with external models which might be legacy code, an IP block, or an implementation of a partially refined system. They are defined formally in order to keep the analyzability of the original framework and also enable automations such as generation of model wrappers and co-simulation interfaces. As a proof of concept, three wrappers for models in different abstraction levels are introduced and implemented for two case studies.
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| 14. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(författare)
-
Formal heterogeneous system modeling with SystemC
- 2012
-
Ingår i: Proceedings of Forum on Specification and Design Languages (FDL) 2012. - 9781467312400 ; , s. 160-167
-
Konferensbidrag (refereegranskat)abstract
- Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. To exploit the benefits of ESL, design languages should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of analysis and synthesis methods; c) executable, to enable early detection of specification; and d) parallel, to exploit the multi- and many-core platforms for simulation and implementation. We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented by the library, which allows the designer to focus on specifying the pure functional aspects. A key advantage is that the formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis.
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| 15. |
- Attarzadeh-Niaki, S. -H, et al.
(författare)
-
Heterogeneous co-simulation for embedded and cyber-physical systems design
- 2020
-
Ingår i: Simulation (San Diego, Calif.). - : SAGE Publications Ltd. - 0037-5497 .- 1741-3133. ; 96:9, s. 753-765
-
Tidskriftsartikel (refereegranskat)abstract
- The growing complexity of embedded and cyber-physical systems makes the design of all system components from scratch increasingly impractical. Consequently, already from early stages of a design flow, designers rely on prior experience, which comes in the form of legacy code or third-party intellectual property (IP) blocks. Current approaches partly address the co-simulation problem for specific scenarios in an ad hoc style. This work suggests a general method for co-simulation of heterogeneous IPs with a system modeling and simulation framework. The external IPs can be integrated as high-level models running in an external simulator or as software- and hardware-in-the-loop simulation with minimal effort. Examples of co-simulation scenarios for wrapping models with different semantics are presented together with their practical usage in two case studies. The presented method is also used to formulate a refinement-by-replacement workflow for IP-based system design.
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| 16. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(författare)
-
Heterogeneous system-level modeling for small and medium enterprises
- 2012
-
Ingår i: Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on. - : IEEE conference proceedings. - 9781467326063 ; , s. 1-6
-
Konferensbidrag (refereegranskat)abstract
- The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol.
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| 17. |
- Attarzadeh-Niaki, Seyed Hosein, et al.
(författare)
-
Integrating Functional Mock-up units into a formal heterogeneous system modeling framework
- 2015
-
Ingår i: 18th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2015. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467380232
-
Konferensbidrag (refereegranskat)abstract
- The Functional Mock-up Interface (FMI) standard defines a method for tool- and platform-independent model exchange and co-simulation of dynamic system models. In FMI, the master algorithm, which executes the imported components, is a timed differential equation solver. This is a limitation for heterogeneous embedded and cyber-physical systems, where models with different time abstractions co-exist and interact. This work integrates FMI into a heterogeneous system modeling and simulation framework as process constructors and co-simulation wrappers. Consequently, each external model communicates with the framework without unnecessary semantic adaptation while the framework provides necessary mechanisms for handling heterogeneity. The presented methods are implemented in the ForSyDe-SystemC modeling framework and tested using a case study.
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| 18. |
- Attarzadeh Niaki, Seyed Hosein, 1984-
(författare)
-
Managing the Complexity in Embedded and Cyber-Physical System Design : System Modeling and Design-Space Exploration
- 2014
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- To cope with the increasing complexity of embedded and cyber-physical system design, different system-level design approaches are proposed which start from abstract models and implement them using design flows with high degrees of automation. However, creating models of such systems and also formulating the mathematical problems arising in these design flows are themselves challenging tasks. A promising approach is the composable construction of these models and problems from more basic entities. Unfortunately, it is non-trivial to propose such compositional formulations today because the current practice in the electronic design automation domain tends to be on using imperative languages and frameworks due to legacy and performance-oriented reasons.This thesis addresses the system design complexity by first promoting proper formalisms and frameworks for capturing models and formulating design-space exploration problems for electronic system-level design in a declarative style; and second, propose realizations based on the industrially accepted languages and frameworks which hold the interesting properties such as composability and parallelism.For modeling, ForSyDe, a denotational system-level modeling formalism for heterogeneous embedded systems is chosen, extended with timed domains to make it more appropriate for capturing cyber-physical systems, and mapped on top of the IEEE standard system design language SystemC. The realized modeling framework, called ForSyDe-SystemC, can be used for modeling systems of heterogeneous nature and their composition to form more sophisticated systems and also conducting parallel and distributed simulation for boosting the simulation speed. Another extension to ForSyDe, named wrapper processes, introduces the ability to compose formal ForSyDe models with legacy IP blocks running in external execution environments to perform a heterogeneous co-simulation.In platform-based design flows, the correct and optimal mapping of an application model onto a flexible platform involves solving a hard problem, named design space exploration. This work proposes Tahmuras, a constraint- based framework to construct generic design space exploration problems as the composition of three individual sub-problems: the application, the platform, and the mapping and scheduling problems. In this way, the model of the design space exploration problem in Tahmuras is automatically generated for each combination of application semantics, target platform, and mapping and scheduling policy simply by composing their respective problems. Using constraint programming, problems can be modeled in a declarative style, while they can be solved in a variety of different styles, including imperative solving heuristics commonly used to solve difficult problems. Efficient parallel solvers exists for constraint programming.
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| 19. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(författare)
-
Rapid virtual prototyping of real-time systems using predictable platform characterizations
- 2013
-
Ingår i: Forum on Specification Design Languages (FDL) 2013. - 9782953050486 ; , s. 6646652-
-
Konferensbidrag (refereegranskat)abstract
- Virtual prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM 2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.
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| 20. |
- Attarzadeh Niaki, Seyed Hosein, et al.
(författare)
-
Semi-formal refinement of heterogeneous embedded systems by foreign model integration
- 2011
-
Ingår i: 2011 Forum on Specification and Design Languages (FDL). - : IEEE conference proceedings. - 9782953050431 ; , s. 179-186
-
Konferensbidrag (refereegranskat)abstract
- There is a need for integration of external models in high-level system design flows. We introduce a set of partial refinement operations to implement models of heterogeneous embedded systems. The models are in form of process networks where each process belongs to a single model of computation. A semi-formal design flow has been introduced based on these operations to incrementally refine system specifications to their implementation. Wrapper processes, which allow co-simulation of a system model in the framework with external models and implementations are used to keep the intermediate system models after each refinement step verifiable. Additionally, this design flow has the advantage of integrating legacy code and IP cores. Using a simple example as the case study, we have shown how we can apply this design methodology to a simple system.
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| 21. |
- Beserra, G. S., et al.
(författare)
-
Integrating virtual platforms into a heterogeneous MoC-based modeling framework
- 2012
-
Ingår i: Proceedings of Forum on Specification and Design Languages (FDL) 2012. - : IEEE conference proceedings. - 9781467312400 ; , s. 143-150
-
Konferensbidrag (refereegranskat)abstract
- In order to handle the increasing complexity of embedded systems, design methodologies must take into account important aspects, such as abstraction, IP-reuse and heterogeneity. System design often starts in a high abstraction level, by developing a virtual platform (VP), which is typically composed of TLM models. TLM has become very popular in the modeling of bus-based systems and currently there is an increasing availability of libraries that provide TLM IPs. Heterogeneity can be naturally captured in a framework supporting different Models of Computation (MoCs). We introduce a novel approach for integrating TLM IPs/VPs into a MoC-based modeling framework, allowing them to co-simulate heterogeneous systems. This approach allows to raise the abstraction level, enabling a more careful design space exploration before selecting a proper VP. We exemplify the potential of our approach with a case study in which a VP with a processor generated by ArchC communicates with a continuous-time model.
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| 22. |
- Björnander, Stefan, 1968-
(författare)
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Methods and Tool Support for Analyzing Architectural Models of Embedded Systems
- 2012
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Embedded systems are ubiquitous in the modern world. They are microcomputers most often included incomplete devices consisting of software and hardware. Embedded systems range from small devices to large systems monitoring and controlling complex processes. Design and development of such systems is a complex task, since embedded systems often need to fulfill extra-functional requirements, on top of functional ones, within constrained amounts of platform resources. Some embedded systems are mission critical; hence, they are not allowed to fail during the mission. One way to ensure that a system works in accordance to its specification is to define the system in an Architecture Description Language (ADL) and apply formal verification methods. The Architecture Design and Analysis Language (AADL) has become popular in the avionic and automobile industry, and is equipped with several annexes, among them the Behavior Annex. However, AADL still misses a formal semantics, which prevents the possibility to prove correctness of architecture features by performing model checking on AADL models. Moreover, AADL does not support time annotations, which prevents modeling of real-time systems in AADL.In this thesis, we address these issues by presenting a formal analysis framework including a denotationalsemantics for a subset of the AADL and its Behavior Annex, which evaluates properties defined in Computation Tree Logic (CTL) by providing model checking. Model checking is a formal verification method that has proved to be powerful as well as effective. Our AADL-semantics is supported by a tool with an implementation of the semantics in Standard ML, which in turn is encapsulated in an Eclipse plugin.We also present a time annotation extension of AADL, implemented in a tool translating time annotated AADL and its Behavior Annex into the Timed Abstract State Machine (TASM) for simulation of real-time features. Another closely related problem is how to achieve optimal component distribution; in order to address this issue we have developed a tool that perform near-optional component distribution in regard to a series of parameters.The research results, which have been validated thought case studies, provides the possibility for a system engineer to model a system and prove its correctness. The research has been conducted in the context of the PROGRESS research center, for predictable embedded software systems.
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| 23. |
- Bonna, Ricardo, et al.
(författare)
-
Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow
- 2019
-
Ingår i: ACM Transactions on Design Automation of Electronic Systems. - : ASSOC COMPUTING MACHINERY. - 1084-4309 .- 1557-7309. ; 24:5
-
Tidskriftsartikel (refereegranskat)abstract
- The tradeoff between analyzability and expressiveness is a key factor when choosing a suitable dataflow model of computation (MoC) for designing, modeling, and simulating applications considering a formal base. A large number of techniques and analysis tools exist for static dataflow models, such as synchronous dataflow. However, they cannot express the dynamic behavior required for more dynamic applications in signal streaming or to model runtime reconfigurable systems. On the other hand, dynamic dataflow models like Kahn process networks sacrifice analyzability for expressiveness. Scenario-aware dataflow (SADF) is an excellent tradeoff providing sufficient expressiveness for dynamic systems, while still giving access to powerful analysis methods. In spite of an increasing interest in SADF methods, there is a lack of formally-defined functional models for describing and simulating SADF systems. This article overcomes the current situation by introducing a functional model for the SADF MoC, as well as a set of abstract operations for simulating it. We present the first modeling and simulation tool for SADF so far, implemented as an open source library in the functional framework ForSyDe. We demonstrate the capabilities of the functional model through a comprehensive tutorial-style example of a RISC processor described as an SADF application, and a traditional streaming application where we model an MPEG-4 simple profile decoder. We also present a couple of alternative approaches for functionally modeling SADF on different languages and paradigms. One of such approaches is used in a performance comparison with our functional model using the MPEG-4 simple profile decoder as a test case. As a result, our proposed model presented a good tradeoff between execution time and implementation succinctness. Finally, we discuss the potential of our formal model as a frontend for formal system design flows regarding dynamic applications.
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| 24. |
- Castañeda Lozano, Roberto, 1986-
(författare)
-
Constraint-Based Register Allocation and Instruction Scheduling
- 2018
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to improve latency or throughput) are central compiler problems. This dissertation proposes a combinatorial optimization approach to these problems that delivers optimal solutions according to a model, captures trade-offs between conflicting decisions, accommodates processor-specific features, and handles different optimization criteria.The use of constraint programming and a novel program representation enables a compact model of register allocation and instruction scheduling. The model captures the complete set of global register allocation subproblems (spilling, assignment, live range splitting, coalescing, load-store optimization, multi-allocation, register packing, and rematerialization) as well as additional subproblems that handle processor-specific features beyond the usual scope of conventional compilers.The approach is implemented in Unison, an open-source tool used in industry and research that complements the state-of-the-art LLVM compiler. Unison applies general and problem-specific constraint solving methods to scale to medium-sized functions, solving functions of up to 647 instructions optimally and improving functions of up to 874 instructions. The approach is evaluated experimentally using different processors (Hexagon, ARM and MIPS), benchmark suites (MediaBench and SPEC CPU2006), and optimization criteria (speed and code size reduction). The results show that Unison generates code of slightly to significantly better quality than LLVM, depending on the characteristics of the targeted processor (1% to 9.3% mean estimated speedup; 0.8% to 3.9% mean code size reduction). Additional experiments for Hexagon show that its estimated speedup has a strong monotonic relationship to the actual execution speedup, resulting in a mean speedup of 5.4% across MediaBench applications.The approach contributed by this dissertation is the first of its kind that is practical (it captures the complete set of subproblems, scales to medium-sized functions, and generates executable code) and effective (it generates better code than the LLVM compiler, fulfilling the promise of combinatorial optimization). It can be applied to trade compilation time for code quality beyond the usual optimization levels, explore and exploit processor-specific features, and identify improvement opportunities in conventional compilers.
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| 25. |
- Castañeda Lozano, Roberto, 1986-
(författare)
-
Integrated Register Allocation and Instruction Scheduling with Constraint Programming
- 2014
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This dissertation proposes a combinatorial model, program representations, and constraint solving techniques for integrated register allocation and instruction scheduling in compiler back-ends. In contrast to traditional compilers based on heuristics, the proposed approach generates potentially optimal code by considering all trade-offs between interdependent decisions as a single optimization problem.The combinatorial model is the first to handle a wide array of global register allocation subtasks, including spill code optimization, ultimate coalescing, register packing, and register bank assignment, as well as instruction scheduling for Very Long Instruction Word (VLIW) processors. The model is based on three novel, complementary program representations: Linear Static Single Assignment for global register allocation; copy extension for spilling, basic coalescing, and register bank assignment; and alternative temporaries for spill code optimization and ultimate coalescing. Solving techniques are proposed that exploit the program representation properties for scalability.The model, program representations, and solving techniques are implemented in Unison, a code generator that delivers potentially optimal code while scaling to medium-size functions. Thorough experiments show that Unison: generates faster code (up to 41% with a mean improvement of 7%) than LLVM (a state-of-the-art compiler) for Hexagon (a challenging VLIW processor), generates code that is competitive with LLVM for MIPS32 (a simpler RISC processor), is robust across different benchmarks such as MediaBench and SPECint 2006, scales up to medium-size functions of up to 1000 instructions, and adapts easily to different optimization criteria.The contributions of this dissertation are significant. They lead to a combinatorial approach for integrated register allocation and instruction scheduling that is, for the first time, practical (it robustly scales to medium-size functions) and effective (it yields better code than traditional heuristic approaches).
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| 26. |
- de Medeiros, Jose. E. G., et al.
(författare)
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An Algebra for Modeling Continuous Time Systems
- 2018
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Ingår i: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE). - : IEEE. - 9783981926309 ; , s. 861-864
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Konferensbidrag (refereegranskat)abstract
- Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine.
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| 27. |
- Diallo, P. I., et al.
(författare)
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A formal, model-driven design flow for system simulation and multi-core implementation
- 2015
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Ingår i: 2015 10th IEEE International Symposium on Industrial Embedded Systems. - : IEEE. - 9781467377119 ; , s. 254-263
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Konferensbidrag (refereegranskat)abstract
- With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.
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| 28. |
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| 29. |
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| 30. |
- Fakih, M., et al.
(författare)
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SAFEPOWER project : Architecture for safe and power-efficient mixed-criticality systems
- 2017
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Ingår i: Microprocessors and microsystems. - : Elsevier. - 0141-9331 .- 1872-9436. ; 52, s. 89-105
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Tidskriftsartikel (refereegranskat)abstract
- With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1.
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| 31. |
- Gorgen, Ralph, et al.
(författare)
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CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
- 2016
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Ingår i: 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016). - : IEEE. - 9781509028160 ; , s. 286-293
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Konferensbidrag (refereegranskat)abstract
- The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.
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| 32. |
- Grüttner, K., et al.
(författare)
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CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
- 2017
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Ingår i: Microprocessors and microsystems. - : Elsevier B.V.. - 0141-9331 .- 1872-9436. ; 51, s. 39-55
-
Tidskriftsartikel (refereegranskat)abstract
- The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).
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| 33. |
- Herrera, F., et al.
(författare)
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An efficient joint analytical and simulation-based design space exploration flow for predictable multi-core systems
- 2015
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Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : ACM Digital Library.
-
Konferensbidrag (refereegranskat)abstract
- Recent work has proposed two-phase joint analytical and simulation-based design space exploration (JAS-DSE) approaches. In such approaches, a first analytical phase relies on static performance estimation and either on exhaustive or heuristic search, to perform a very fast filtering of the design space. Then, a second phase obtains the Pareto solutions after an exhaustive simulation of the solutions found as compliant by the analytical phase. However, the capability of such approaches to find solutions close to the actual Pareto set at a reasonable time cost is compromised by current system complexities. This limitation is due to the fact that such approaches do not support an heuristic exploration on the simulation-based phase. It is not straightforward because in the second phase the heuristic is constrained to consider only the custom set of solutions found in the first phase. This set is in general unconnected and irregularly distributed, which prevents the application of existing heuristics. This paper provides as a solution a novel search heuristic called ARS (Adaptive Random Sampling). The ARS strategy enables the application of heuristic search in the two phases of the JAS-DSE flow, by enabling the application of heuristic in the second phase, regardless the type of performance estimation done at each phase. Moreover, it enables the definition of N-phase DSE flows. The paper shows on an experiment focused on predictable multi-core systems how this enhanced JAS-DSE is capable to find more efficient solutions and to tune the trade-off between exploration time and accuracy in finding actual Pareto solutions.
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| 34. |
- Herrera, Fernando, et al.
(författare)
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An extensible infrastructure for modeling and time analysis of predictable embedded systems
- 2015
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Ingår i: Forum on Specification and Design Languages. - : IEEE Computer Society. - 9791092279078
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Konferensbidrag (refereegranskat)abstract
- Efficient design of predictable systems on top of multiprocessor-based architectures is challenging. It demands an integration effort to support system models relying on Models-of-Computation (MoC) theory, supporting real-time (RT) analysis and electronic system-level (ESL) design techniques. This paper presents a SystemC-based framework for modelling and time analysis of predictable embedded systems which aims such an integration. The framework has features for system-level design and research of predictable systems. Moreover, the framework is extensible, to enable experts from different communities to explore and assess their contributions, e.g. new schedulers, schedulability analyses, and predictable platform components, without having to rely on a physical platform.
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| 35. |
- Herrera, Fernando, et al.
(författare)
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Combining analytical and simulation-based design space exploration for efficient time-critical and mixed-criticality systems
- 2015
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Ingår i: Forum on Specification and Design Languages, FDL 2013. - Cham : Springer International Publishing. - 9783319063164 ; , s. 167-188
-
Konferensbidrag (refereegranskat)abstract
- In the context of the design on time-critical systems, analytical models with worst case workloads are used to identify safe solutions that guarantee hard timing constraints. However, the focus on the worst case often leads to unnecessarily pessimistic and inefficient solutions, in particular for mixed-critical systems. To overcome the situation, the paper proposes a novel design flow integrating analytical and simulation-based Design Space Exploration (DSE). This combined approach is capable to find more efficient design solutions, without sacrificing timing guarantees. For it, a first analytical DSE phase obtains a set of solutions compliant with the critical time constraints. Search of the Pareto optimum solutions is done among this set, but it is delegated to a second simulation-based search. The simulation-based search enables more accurate estimations, and the consideration of a specific (or an average-case) scenario. The chapter shows that this can lead to different Pareto sets which reflect improved design decisions with respect to a pure analytical DSE approach, and which are found faster than through a pure simulation-based DSE approach. This is illustrated through an accompanying example and a proof-of-concept implementation of the proposed DSE flow.
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| 36. |
- Herrera, Fernando, 1975-, et al.
(författare)
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Combining Analytical and Simulation-based Design Space Exploration for Time-Critical Systems
- 2013
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Ingår i: Forum on Specification & Design Languages (FDL), 2013. - : IEEE conference proceedings. - 9782953050486 ; , s. 6646657-
-
Konferensbidrag (refereegranskat)abstract
- In the context of the design on time-critical systems, analytical models with worst case workloads are used to identify safe solutions that guarantee hard timing constraints. However, the focus on the worst case often leads to unnecessarily pessimistic and inefficient solutions, in particular for mixed-critical systems. To overcome the situation, the paper proposes a novel design flow integrating analytical and simulation-based design space exploration (DSE). This combined approach is capable to find more efficient design solutions, without sacrificing timing guarantees. For it, a first analytical DSE phase obtains a set of solutions compliant with the critical time constraints. Search of the optimum solution is done among this set, but it is delegated to a second simulation-based search, for fine tuning and average-case optimisation. The potential of our approach is illustrated by a proof-of-concept implementation of the proposed DSE flow and an accompanying DSE example.
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| 37. |
- Herrera, Fernando, et al.
(författare)
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Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems
- 2013
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Ingår i: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013. - : IEEE conference proceedings. - 9780769550749 ; , s. 989-996
-
Konferensbidrag (refereegranskat)abstract
- Mixed-criticality system (MCS) design is an emerging discipline, which has been identified as a core foundational concept in fields such as cyber-physical systems. The hard real-time design community has pioneered the contributions to MCS design, extending scheduling theory to consider mixed-criticalities and the impact of on-chip and off-chip communication infrastructures. However, the development of MCS design methodologies capable to provide safe and efficient solutions for complex applications and platforms in an acceptable design time demands a more interdisciplinary approach. This paper is a first step towards such an approach in the development of MCS design methodologies. The paper first identifies main design disciplines to be involved in MCS design, both at SoC and system-of-systems (SoS) scales. Then, the paper proposes a core ontology for modelling a mixed-criticality system at both SoC scale (MCSoC) and SoS scale (MCSoS). Finally, the paper introduces a set of aspects required for MCS design which have been identified as open and challenging attending the overviewed state-of-the-art.
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| 38. |
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| 39. |
- Herrholz, Andreas, et al.
(författare)
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The ANDRES Project : Analysis and Design of run-time Reconfigurable, heterogeneous Systems
- 2007
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Ingår i: Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. - : IEEE. - 9781424410606 - 1424410606 ; , s. 396-401
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Konferensbidrag (refereegranskat)abstract
- Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task due to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.
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| 40. |
- Hjort Blindell, Gabriel, et al.
(författare)
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Synthesizing Code for GPGPUs from abstract formal models
- 2016
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Ingår i: 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014. - Cham : Springer. ; , s. 115-134
-
Konferensbidrag (refereegranskat)abstract
- Today multiple frameworks exist for elevating the task of writing programs for GPGPUs, which are massively data-parallel execution platforms. These are needed as writing correct and high-performing applications for GPGPUs is notoriously difficult due to the intricacies of the underlying architecture. However, the existing frameworks lack a formal foundation that makes them difficult to use together with formal verification, testing, and design space exploration. We present in this chapter a novel software synthesis tool—called f2cc—which is capable of generating efficient GPGPU code from abstract formal models based on the synchronous model of computation. These models can be built using high-level modeling methodologies that hide low-level architecture details from the developer. The correctness of the tool has been experimentally validated on models derived from two applications. The experiments also demonstrate that the synthesized GPGPU code yielded a 28× speedup when executed on a graphics card with 96 cores and compared against a sequential version that uses only the CPU.
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| 41. |
- Hjort Blindell, Gabriel, et al.
(författare)
-
Synthesizing Code for GPGPUs from Abstract Formal Models
- 2014
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Ingår i: Forum on specification and Design Languages (FDL), Munich, Germany, October 14-16, 2014. - : IEEE conference proceedings. - 9782953050493
-
Konferensbidrag (refereegranskat)abstract
- Today multiple frameworks exist for elevating thetask of writing programs for GPGPUs, which are massively data-parallel execution platforms. These are needed as writing correctand high-performing applications for GPGPUs is notoriouslydifficult due to the intricacies of the underlying architecture.However, the existing frameworks lack a formal foundation thatmakes them difficult to use together with formal verification,testing, and design space exploration. We present in this papera novel software synthesis tool – called f2cc – which is capableof generating efficient GPGPU code from abstract formal modelsbased on the synchronous model of computation. These modelscan be built using high-level modeling methodologies that hidelow-level architecture details from the developer. The correctnessof the tool has been experimentally validated on models derivedfrom two applications. The experiments also demonstrate that thesynthesized GPGPU code yielded a 28× speedup when executedon a graphics card with 96 cores and compared against asequential version that uses only the CPU.
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| 42. |
- Jakobsen, M. K., et al.
(författare)
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System level modelling with open source tools
- 2011
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Ingår i: Embedded World Conference 2011.
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Konferensbidrag (refereegranskat)abstract
- In this paper, we present a system level designmethodology which allows designers to model andanalyze their systems from the early stages of thedesign process until nal implementation. The de-sign methodology targets heterogeneous embeddedsystems and is based on a formal modeling frame-work, called ForSyDe. ForSyDe is available underthe open Source approach, which allows small andmedium enterprises (SME) to get easy access toadvanced modeling capabilities and tools. We givean introduction to the design methodology throughthe system level modeling of a simple industrial usecase, and we outline the basics of the underlyingForSyDe model.
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| 43. |
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| 44. |
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| 45. |
- Jantsch, Axel, et al.
(författare)
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Models of computation and languages for embedded system design
- 2005
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Ingår i: IEE Proceedings - Computers and digital Techniques. - : Institution of Engineering and Technology (IET). - 1350-2387 .- 1359-7027. ; 152:2, s. 114-129
-
Tidskriftsartikel (refereegranskat)abstract
- Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete time, synchronous and untimed MoCs are distinguished. System level models serve a variety of objectives with partially contradicting requirements. Consequently, it is argued that different MoCs are necessary for the various tasks and phases in the design of an embedded system. Moreover, different MoCs have to be integrated to provide a coherent system modelling and analysis environment. The relation between some popular languages and the reviewed MoCs is discussed to find that a given MoC is offered by many languages and a single language can support multiple MoCs. It is contended that it is of importance for the quality of tools and overall design productivity, which abstraction levels and which primitive operators are provided in a language. However, it is observed that there are various flexible ways to do this, e.g. by way of heterogeneous frameworks, coordination languages and embedding of different MoCs in the same language.
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| 46. |
- Jantsch, Axel, et al.
(författare)
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Models of Computation in the Design Process
- 2006
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Ingår i: System-on-Chip. - : Institution of Engineering and Technology. - 9780863415524 ; , s. 161-185
-
Bokkapitel (refereegranskat)
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| 47. |
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| 48. |
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| 49. |
- Jordao, Rodolfo, et al.
(författare)
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A multi-view and programming language agnostic framework for model-driven engineering
- 2022
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Ingår i: PROCEEDINGS OF THE 2022 FORUM ON SPECIFICATION & DESIGN LANGUAGES (FDL). - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- Model-driven engineering (MDE) addresses the complexity of modern-day embedded system design. Multiple MDE frameworks are often integrated into a design process to use each MDE framework's state-of-the-art tools for increased productivity. However, this integration requires substantial development effort. In this paper, we propose an MDE, framework based on a formalism of system graphs and trait hierarchies for programming-language-agnostic integration between tools within our framework and with tools of other MDE frameworks. Implementing our framework for each programming language is a one-time development effort. We evaluate our proposal in an MDE design process by developing a Java supporting library and an AMALTHEA connector. Then we perform an MDE, industrial avionics case study with both. The evaluation shows that our framework facilitates the integration of different tools and the independent development of different system parts. Therefore, our framework is a reliable MDE, framework that lowers the effort of integrating tools to benefit from their combined state-of-the-art.
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| 50. |
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