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Träfflista för sökning "WFRF:(Seceleanu T.) "

Sökning: WFRF:(Seceleanu T.)

  • Resultat 1-14 av 14
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1.
  • Seceleanu, T., et al. (författare)
  • Messge from the ECPE Organizing Committee
  • 2016
  • Ingår i: Proceedings - International Computer Software and Applications Conference. ; , s. 281-
  • Konferensbidrag (refereegranskat)
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2.
  • Afzal, Wasif, et al. (författare)
  • Program committee for icse 2018 posters track
  • 2018
  • Ingår i: Proceedings / International Conference of Software Engineering. - : IEEE Computer Society. - 0270-5257 .- 1558-1225. ; Part F137351
  • Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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3.
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5.
  • Buiu, C, et al. (författare)
  • GENESIS - A Framework for Global Engineering of Embedded Systems
  • 2008
  • Ingår i: Proceedings - International Conference on Software Engineering. - New York, NY, USA : ACM. - 9781605580760 ; , s. 87-93
  • Konferensbidrag (refereegranskat)abstract
    • GENESIS is an European initiative involving institutions and personsfrom older and new EU members, and West Balkan countries. It aims atdeveloping a global network of research and education in embeddedsystems. The related research will be coordinated in such a way toaddress hot topics at European and global levels and willconcentrate on the fusion of embedded systems and distributedservices over the Internet. One of the main objectives of GENESIS isto develop a distributed virtual laboratory to be used in embeddedsystems research and education and this is described in detail. Thispaper presents the rationale behind this initiative and the mainactions that are proposed to fulfill the educational, and scientificobjectives of GENESIS.
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6.
  • Halilovic, Amar, et al. (författare)
  • Multi-constrained Network Occupancy Optimization
  • 2021
  • Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : Association for Computing Machinery. - 9781450390576
  • Konferensbidrag (refereegranskat)abstract
    • The greater the number of devices on a network, the higher load in the network, the more chance of a collision occurring, and the longer it takes to transmit a message. The size of load can be identified by measuring the network occupancy, hence it is desirable to minimize the latter. In this paper, we present an approach for network occupancy minimization by optimizing the packing process while satisfying multiple constraints. We formulate the minimization problem as a bin packing problem and we implement a modification of the Best-Fit Decreasing algorithm to find the optimal solution. The approach considers grouping signals that are sent to different destinations in the same package. The analysis is done on a medium-sized plant model, and different topologies are tested. The results show that the proposed solution lowers the network occupancy compared to a reference case.
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7.
  • Kofroň, J., et al. (författare)
  • Preface
  • 2024
  • Ingår i: Lecture Notes in Computer Science. - : Springer Science and Business Media Deutschland GmbH. - 9783031492518
  • Konferensbidrag (refereegranskat)
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8.
  • Latif, K., et al. (författare)
  • Application development flow for on-chip distributed architectures
  • 2008
  • Ingår i: 2008 IEEE International SOC Conference, SOCC. - 9781424425969 ; , s. 163-168
  • Konferensbidrag (refereegranskat)abstract
    • We approach the construction of design methodologies for on-chip multiprocessor platforms, with the focus on the SegBus, a segmented bus platform. We study how applications can be mapped on such distributed architecture and show how to build the concrete level software procedures that will coordinate the control flow on the platform. The approach employs models developed in the Matlab-Simulink environment considering also a unified representation of both platform and application. The running example is represented by the H.264 encoder. Allocation of processing elements on the platform, structure and functionality and the eventual control code for arbiters are the in topics described here.
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9.
  • Niazi, M. F., et al. (författare)
  • A DSL for the SegBus platform
  • 2009
  • Ingår i: IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS. ; , s. 393-398
  • Konferensbidrag (refereegranskat)abstract
    • The paper presents a Domain Specific Language (DSL) for a multi-core segmented bus platform, SegBus. The DSL, based on a UML profile, consists of graphical platform elements in the form of stereotypes with the necessary tagged values to depict platform aspects at high level of abstraction. Customizations are applied to each stereotyped element in the form of user-defined rules to restrict relationship between platform elements. The Object Constraint Language (OCL) is employed to introduce constraints, in order to impose structural requirements between platform elements, for which we introduce mechanisms to validate them. We present a simplified example of a H.264 video encoder application where the DSL is used to specify and validate application and platform model in a unified representation manner.
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10.
  • Niazi, M. F., et al. (författare)
  • An automated control code generation approach for the SegBus platform
  • 2010
  • Ingår i: Proceedings - IEEE International SOC Conference, SOCC 2010. ; , s. 199-204
  • Konferensbidrag (refereegranskat)abstract
    • We present here a model-driven approach for the generation of low-level control code for the arbiters, to support application implementation and scheduled execution on a multi-core segmented bus platform, SegBus. The approach considers Model-Driven Architecture as a key to model the application at two different abstraction levels, namely as Packet-Synchronous Dataflow and Platform Specific Model, using the SegBus platform's Domain Specific Language. Both models are transformed into Extensible Markup Language schemes, and then utilized by an emulator program to generate the application-dependent VHDL code, the so-called snippets. The obtained code is inserted in a specific section of the platform arbiters. We present an example of a simplified stereo MP3 decoder where the methodology is employed to generate the control code of arbiters.
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11.
  • Niazi, M. F., et al. (författare)
  • An Emulation Solution for the SegBus Platform
  • 2010
  • Ingår i: 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, ECBS 2010. - : IEEE. ; , s. 268-275
  • Konferensbidrag (refereegranskat)abstract
    • The paper presents an emulation solution for a multi-core segmented bus platform, SegBus, to assess the performance aspects of any specific application on a particular platform configuration, modeled in UML. We present method to transform Platform Specific Model (PSM) of application into Java source code using modeling tool and how the generated code can be utilized by the emulator program to get the execution results. The solution enables us to estimate performance aspects with different platform configurations together with the application at early stages of the design process.
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12.
  • Nita, Iulian, et al. (författare)
  • Multiprocessor real time edge detection using FPGA IP cores
  • 2011
  • Ingår i: Proceedings - 2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, ICCP 2011. - 9781457714788 ; , s. 331-334
  • Konferensbidrag (refereegranskat)abstract
    • Real time edge detection is required in many embedded systems where execution speed is critical. This task is intensely computational but highly parallelizable and, in order to satisfy the real-time requirements, using multiprocessor-based embedded systems can be a viable solution. In this paper we propose a MPSoC hardware and software co-design method for real-time Sobel edge detection using FPGA and IP blocks. The experiments we performed show a speed-up of 1.71 in the case of a multiprocessor system with two processors and a speed-up of 3.48 in the case of a multiprocessor system with four processing cores, versus a single processor system
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13.
  • Sapienza, G., et al. (författare)
  • System Level Partitioning for Embedded Systems
  • 2017
  • Ingår i: Proceedings International Computer Software and Applications Conference. - 0730-3157. - 9781538603673 ; 2, s. 597-602
  • Konferensbidrag (refereegranskat)abstract
    • Platforms with different computation resource, e.g. CPUs and FPGAs, become one of the first choices to deploy performance-requiring embedded applications. On this technology, functionalities can be implemented either as hardware (HW) or software (SW) components. Here, we extend the MultiPar methodology to support the selection of optimal partitioning solutions with respect to system properties. We show the feasibility of the proposed methodology and validate the composition rules for properties used in the partitioning decision process.
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14.
  • Truscan, D., et al. (författare)
  • Towards a Design Methodology for Multiprocessor Platforms
  • 2007
  • Ingår i: COMPSAC 2007. ; , s. 575-578
  • Konferensbidrag (refereegranskat)abstract
    • We discuss a design methodology for SegBus, a multicore segmented bus platform. The methodology supports the modeling of the platform at several abstraction levels, enabling the designer to focus only on the relevant aspects of the architecture at a given development stage. We employ the Unified Modeling Language (UML) as a specification language for the SegBus platform and we customize its elements to serve our specific purposes via the profiling mechanism. The approach enables us to take advantage of graphical models of the platform and of automated refinements of these models towards implementation.
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  • Resultat 1-14 av 14

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