| 1. |
|
|
| 2. |
|
|
| 3. |
- Andersson, Oskar, et al.
(författare)
-
Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
- 2013
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub- VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D- latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220mV) and a total energy of 14fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65 nm CMOS reported to date.
|
|
| 4. |
|
|
| 5. |
- Meinerzhagen, Pascal, et al.
(författare)
-
Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
- 2011
-
Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - 2156-3365. ; 1:2, s. 173-182
-
Tidskriftsartikel (refereegranskat)abstract
- In this paper, standard-cell based memories (SCMs)are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.
|
|
| 6. |
|
|
| 7. |
|
|
| 8. |
|
|
| 9. |
- Mohammadi, Babak, et al.
(författare)
-
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
- 2014
-
Ingår i: [Host publication title missing].
-
Konferensbidrag (refereegranskat)abstract
- The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power
|
|
| 10. |
- Mohammadi, Babak, et al.
(författare)
-
Sizing of Dual-V-T Gates for Sub-V-T Circuits
- 2012
-
Ingår i: 2012 IEEE Subthreshold Microelectronics Conference (SubVT). - 9781467315869
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.
|
|
| 11. |
- Nilsson, Peter, et al.
(författare)
-
Power Savings in Digital Filters for Wireless Communication
- 2013
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static power consumption, the silicon area, as well as the delay time are reduced substantially, without any need for trade-offs. The overall improvements in area, power consumption, and delay time, are around 50%, at an average.
|
|
| 12. |
- Nilsson, Peter, et al.
(författare)
-
Supply-Voltage Down Conversion for Digital CMOS Designs
- 2014
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a methodology to reduce the power consumption, by using multiple supply voltage levels. The voltage levels are scaled down from a single supply voltage, by the use of a diode-connected device. Only one single device is used per conversion, which gives a small area overhead. No inductors and no off-chip components are used. The methodology is tested on different constellations of inverters and on anti-aliasing filters. A power reduction down to 47% in the filters with reduced supply voltage and down to 72% in the complete filter is shown.
|
|
| 13. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
- 2012
-
Ingår i: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012). - 9781467312615 - 9781467312615
-
Konferensbidrag (refereegranskat)abstract
- Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavors are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.
|
|
| 14. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
A Digital Baseband for Low Power FSK Based Receiver in 65 nm CMOS
- 2014
-
Ingår i: [Host publication title missing].
-
Konferensbidrag (refereegranskat)abstract
- The design of a digital baseband for a low power wireless receiver in 65 nm CMOS is presented. It consists of decimation filtering, matched filters for data detection, and preamble based synchronization. The circuit was designed using low threshold devices in both low power (LP-LVT) and general-purpose (GP-LVT) domains. The fabricated circuits were functionally verified, and silicon measurements show a minimum energy dissipation of around 454 pJ and 708 pJ per output bit at a rate of 500 kbit/s for the LP-LVT and GP-LVT implementations, respectively.
|
|
| 15. |
|
|
| 16. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
- 2011
-
Ingår i: 2011 IEEE International Symposium on Circuits and Systems (ISCAS). - 2158-1525 .- 0271-4310. ; , s. 837-840
-
Konferensbidrag (refereegranskat)abstract
- This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250Ksamples/s and 2Msamples/s, at a supply voltage of 260mV. The total energy dissipation of the filter is 205 fJ per sample.
|
|
| 17. |
- Sherazi, Syed Muhammad Yasser
(författare)
-
Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation
- 2013
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The ever expanding market of ultra portable electronic products is compelling the designer to invest major efforts in the development of small and low energy electronic devices. The driving force and benefactors of such devices are (but not limited to) e-health system, sensor network applications, security systems, environmental applications, and home automation systems. These markets have launched a massive trend towards ultra low-energy and ultra low-voltage devices. As the technology scales, the dimensions of a transistors have become extremely small, leading to reliability and process variation issues. Above all, with the ability of placing millions of gates in a small area, high current consumption have become one of the key factors in modern high-performance technologies. In portable electronics, the battery life time is a major issue, as most of the time the device is accompanied with an enclosed battery that has to last for long periods without compromise on performance. Furthermore, there are many applications where the battery lifetime sets the lifetime of the device. Therefore, research is needed to identify the techniques and the impact of them on the design operated for ultra low-energy. The low energy dissipation requirements on a design are achievable by employing various optimization techniques. Voltage scaling is the most effective knob to reduce energy dissipation. For this reason ultra-low energy design usually translates into ultra-low voltage or subthreshold (sub-VT) domain operation. This work presents an analysis on design space for ultra-low energy dissipation of digital circuits. The circuits are operated in the sub-VT region with moderate throughput constraints. The drawback of operating circuits in sub-VT is slow speed performances and reduced reliability. To combat speed degradation due to scaling of the supply voltage, the architectural design space, needs exploration. Techniques such as device sizing, body biasing, stacking transistors, dual threshold gates, multi threshold synthesis, pipelining, and loop unfolding, are explored and applied to the designs. The designs are synthesized in a 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as multi-VT designs. A sub-VT energy model is applied to characterize the designs in the sub- VT domain. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The minimum reliable operation voltage (ROV) for gates in low power 65 nm CMOS technology is found to be around 250 mV. The applied energy model for designs to be characterized for sub-VT domain operation is presented. The energy model encompasses single VT implementations and multi- VT implementations. The energy modeling is based on the 65 nm CMOS standard cells provided by the technology vendor. The energy model has been used to evaluate various techniques and constraints for a circuits operated in the sub-VT domain. The work describes how the energy dissipation of architectures vary w.r.t. switching activity, e. The effects of pipelining together with supply voltage scaling is analyzed, which shows that they have high benefits with respect to energy dissipation. Various half-band digital (HBD) filter structures are evaluated for minimum energy dissipation in the sub-VT domain for a throughput constrained system. All architectures, i.e., unfolded and the basic HBD filter, are implemented and simulated using 65 nm Low-Power High-Threshold (HVT) standard cells. The application of a sub-VT energy model reveals that it is beneficial to use an unfolded implementation to achieve low energy dissipation per sample at EMV, when compared to the energy dissipated by a basic simplified HBD filter implementation. Various available threshold options are analyzed with the help of filter structures by using 65 nm Low-Leakage High-Threshold (HVT), Standard-Threshold (SVT) and Low-Threshold (LVT) standard cells. Secondly, the design space is increased by utilization of a combination of HVT + SVT and also HVT + LVT cells. The analysis with sub-VT energy model leads to the conclusion that a suitable design is a synergy between parallelism, and utilization of various threshold options. In this analysis the multi-VT, implementations did not show a major advantage over single VT implementations. A decimation filter chain consisting of 4 HBD filters is fabricated and the silicon measurements demonstrate that SVT and different architectural flavors are suitable for a ultra low energy (ULE) implementation. Silicon measurements prove functionality down to a supply at 350 mV, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle. Additionally, an alternative to SRAM macro is presented for sub-VT operations. The memory is based on standard-cells and is referred to as SCMs. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT energy characterization model.
|
|
| 18. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
- 2010
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This manuscript presents simulation results of energy dissipation in sub-threshold (sub-VT ) of various 16-bit adder structures. The architectures designed for the comparative experiments are, a bit-serial, an 8-bit digit-serial and a 16-bit parallel adder structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. The results show that an energy minimum operating voltage exists for all the three implementations, however the 8-bit digit serial has the least energy minimum operating point. The advantage of the bit-serial structure is that by employing this technique we may save 88% area when compared to parallel implementation and 66% area when compared to digital-serial implementation.
|
|
| 19. |
|
|
| 20. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
Reduction of Substrate Noise in Sub Clock Frequency Range
- 2010
-
Ingår i: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. - : IEEE. - 1549-8328. ; 57:6, s. 1287-1297
-
Tidskriftsartikel (refereegranskat)abstract
- We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.
|
|
| 21. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
- 2013
-
Ingår i: Microprocessors and Microsystems. - : Elsevier BV. - 0141-9331. ; 37:4-5, s. 494-504
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents an analysis of energy dissipation of a decimation filter chain of four half band digital (HBD) filters operated in the sub-threshold (sub-VT) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as dual-VT. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. Simulation results show that the unfolded by 2 and 4 architectures are the most energy efficient for throughput requirements between 250 ksamples/s, and 2Msamples/s. By the selection of optimum architectures and standard cells, at the required throughput the simulated minimum energy dissipation for the required throughput per output sample is 164 fJ and 205 fJ, with single supply voltage of 260mV.
|
|
| 22. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
- 2010
-
Ingår i: [Host publication title missing]. - 9781424489725
-
Konferensbidrag (refereegranskat)abstract
- This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub- VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of 100Ksamples/sec to 1Msamples/s, as it dissipates less energy than any other implementation in this speed range.
|
|
| 23. |
|
|
| 24. |
- Sjöland, Henrik, et al.
(författare)
-
Ultra low power transceivers for wireless sensors and body area networks
- 2014
-
Ingår i: 2014 8th International Symposium on Medical Information and Communication Technology (ISMICT). - 2326-828X. - 9781479948567
-
Konferensbidrag (refereegranskat)abstract
- A transceiver suitable for devices in wireless body area networks is presented. Stringent requirements are imposed by the high link loss between opposite sides of the body, about 85 dB in the 2.45 GHz ISM band. Despite this, minimum physical size and power consumption are required, and we target a transceiver with 1 mm2 chip area, 1 mW active power consumption, and data rate 250 kbit/s. The receiver is fully integrated., fabricated and measured in 65-nm CMOS, and size and power consumption are carefully considered at all levels of circuit and system design. The modulation is frequency shift keying, chosen because transmitters can be realized with high efficiency and low spurious emissions; a modulation index 2 creates a midchannel spectral notch. A direct-conversion receiver achieves minimum power consumption. A tailored demodulation structure makes the digital baseband compact and low power. The channel decoder has been implemented in both analog and digital domains to find the most power efficient solution. Antenna design and wave propagation are studied via simulations with phantoms. The 2.45 GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme based on a duty-cycled wake-up receiver is designed.
|
|
