SwePub - search: WFRF:(Svensson Bertil)

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1.	Svensson, Per Anders, 1959, et al. (author) Identification of genes predominantly expressed in human macrophages 2004 In: Atherosclerosis. - : Elsevier BV. ; 177, s. 287-290 Journal article (peer-reviewed)abstract Identification of cell and tissue specific genes may provide novel insights to signaling systems and functions. Macrophages play a key role in many diseases including atherosclerosis. Using DNA microarrays we compared the expression of approximately 10,000 genes in 56 human tissues and identified 23 genes with predominant expression in macrophages. The identified genes include both genes known to be macrophage specific and genes previously not well described in this cell type. Tissue distribution of two genes, liver X receptor (LXR) alpha and interleukin-1 receptor antagonist (IL1RN), was verified by real-time RT-PCR. We conclude that comparison of expression profiles from a large number of tissues can be used to identify genes that are predominantly expressed in certain tissues. Identification of novel macrophage specific genes may increase our understanding of the role of this cell in different diseases.
2.	Svensson, Per-Arne, 1969, et al. (author) Regulation and splicing of scavenger receptor class B type I in human macrophages and atherosclerotic plaques 2005 In: BMC Cardiovasc Disord. - : Springer Science and Business Media LLC. - 1471-2261. ; 5 Journal article (peer-reviewed)abstract BACKGROUND: The protective role of high-density lipoprotein (HDL) in the cardiovascular system is related to its role in the reverse transport of cholesterol from the arterial wall to the liver for subsequent excretion via the bile. Scavenger receptor class B type I (SR-BI) binds HDL and mediates selective uptake of cholesterol ester and cellular efflux of cholesterol to HDL. The role of SR-BI in atherosclerosis has been well established in murine models but it remains unclear whether SR-BI plays an equally important role in atherosclerosis in humans. The aim of this study was to investigate the expression of SR-BI and its isoforms in human macrophages and atherosclerotic plaques. METHODS: The effect of hypoxia and minimally modified low-density lipoprotein (mmLDL), two proatherogenic stimuli, on SR-BI expression was studied in human monocyte-derived macrophages from healthy subjects using real-time PCR. In addition, SR-BI expression was determined in macrophages obtained from subjects with atherosclerosis (n = 15) and healthy controls (n = 15). Expression of SR-BI isoforms was characterized in human atherosclerotic plaques and macrophages using RT-PCR and DNA sequencing. RESULTS: SR-BI expression was decreased in macrophages after hypoxia (p < 0.005). In contrast, SR-BI expression was increased by exposure to mmLDL (p < 0.05). There was no difference in SR-BI expression in macrophages from patients with atherosclerosis compared to controls. In both groups, SR-BI expression was increased by exposure to mmLDL (p < 0.05). Transcripts corresponding to SR-BI and SR-BII were detected in macrophages. In addition, a third isoform, referred to as SR-BIII, was discovered. All three isoforms were also expressed in human atherosclerotic plaque. Compared to the other isoforms, the novel SR-BIII isoform was predicted to have a unique intracellular C-terminal domain containing 53 amino acids. CONCLUSION: We conclude that SR-BI is regulated by proatherogenic stimuli in humans. However, we found no differences between subjects with atherosclerosis and healthy controls. This indicates that altered SR-BI expression is not a common cause of atherosclerosis. In addition, we identified SR-BIII as a novel isoform expressed in human macrophages and in human atherosclerotic plaques.
3.	Alam, Ashraful, et al. (author) Parallelization of the Estimation Algorithm of the 3D Structure Tensor 2012 In: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012. - Piscataway, N.J. : IEEE Press. - 9781467329194 - 9781467329217 Conference paper (peer-reviewed)abstract The three dimensional structure tensor algorithm (3D-STA) is often used in image processing applications to compute the optical flow or to detect local 3D structures and their directions. This algorithm is computationally expensive due to many computations that are required to calculate the gradient, the tensor, and to smooth every pixel of the image frames. Therefore, it is important to parallelize the implementation to achieve high performance. In this paper we present two parallel implementations of 3D-STA; namely moderately parallelized and highly parallelized implementation, on a massively parallel reconfigurable array. Finally, we evaluate the performance of the generated code and results are compared with another optical flow implementation. The throughput achieved by the moderately parallelized implementation is approximately half of the throughput of the Optical flow implementation, whereas the highly parallelized implementation results in a 2x gain in throughput as compared to the optical flow implementation. © 2012 IEEE.
4.	Almén, Oscar, 1970-, et al. (author) Kina idag 2008 Book (pop. science, debate, etc.)
5.	Almgren Mason, Suzanne, et al. (author) Bridging Scientific Cultures in a Regional Health Care Context 2010 In: VIII Triple Helix International Conference on University, Industry and Government Linkages. Conference paper (other academic/artistic)abstract Embedded Intelligent Systems (EIS) is the joint research field of the four collaborating laboratories at the School of Information Science, Computer and Electrical Engineering (IDE) at Halmstad University. The research of the four labs is integrated into a strong concerted research environment within embedded systems (EIS) - with a perspective reaching from the enabling technology via new system solutions and intelligent applications to end user aspects and business models. It is an expanding research area with many applications, not least ones that exist in everyday life.EIS is an important research environment contributing to the regional Triple Helix innovation system Healthcare Technology which the region has pointed out as a prioritised development sector. With its strong connections to both established and new, expanding firms hived off from the university, the research environment is active in the Healthcare Technology Alliance, a network of around sixty companies, counties and health care providers in south-western Sweden with the aim of developing the region into a leading arena for the development of health technology products and services. Several projects together with these participants concern both research and technology transfer.An integrated gender and gender equality perspective in innovations within the health technology area is necessary in order to be able to meet the needs of an ageing population with quality innovations. The relevancy of a gender perspective is clear in relation to the fact that about 70% of all those older than 75 years are women. Older women are on average cared for in hospital twice as long as men, partly due to differing disease panoramas, but also because men are more often cared for in the home by a woman while the women who live longer more often live alone. With the expansion of home-help and home nursing new needs follow and it is likely that a gender perspective will become necessary for the development of products and services that can make daily life easier for the elderly. The gender perspective also has relevance from the point of view of care staff. New technology is developed for application within the health and care sector where the larger professional groups consist mainly of women. The technology, most often designed by men, is used by women. With this in mind it is clear that an important aspect of good innovations is that the end users are involved in the innovation process.Based on an awareness of the need for a more articulated gender perspective within the research environment, in order to meet the needs expressed above, an application for a gender inclusive R&D project was handed in to the VINNOVA programme Applied Gender Research in Strong Research and Innovation Environments. The G-EIS project (Gender Perspective on Embedded Intelligent Systems - Application in Healthcare Technology) was approved and started in 2009. The project involves researchers from the EIS research environment as well as representatives from companies and the public sector.The project participants are on the whole agreed on the need for a gender perspective in the R&I environment, but struggle with the meeting of two epistemologically opposed theories of science. The understanding within gender studies that research and production both create reality and are informed by it is not always accepted within the areas of natural science. Engineering and other technological sciences not only consider aspects of science to be separate from reality, but also seek positivistic proof in research, something not always possible in the more qualitative research of the social sciences. Researching how these two perspectives meet within this specific project is the topic of this paper.
6.	Axelsson, Michael, 1958, et al. (author) Hållning av zebrafisk i försöksdjursanläggningar 2016 Reports (other academic/artistic)
7.	Bengtsson, Jerker, et al. (author) A configurable framework for stream programming exploration in baseband applications 2006 In: 2006 IEEE International Parallel & Distributed Processing Symposium. - Piscataway, N.J. : IEEE Press. - 1424400546 ; , s. 8- Conference paper (peer-reviewed)abstract This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.
8.	Bengtsson, Jerker, et al. (author) A Domain-specific Approach for Software Development on Manycore Platforms 2008 In: SIGARCH Computer Architecture News. - New York : ACM Press. - 0163-5964 .- 1943-5851. ; 36:5, s. 2-10 Journal article (peer-reviewed)abstract The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.
9.	Bengtsson, Jerker, et al. (author) Machine Assisted Code Generation for Manycore Processors 2007 In: Proceedings of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden - RTiS'07). ; , s. 9- Conference paper (peer-reviewed)
10.	Bengtsson, Jerker, et al. (author) Manycore performance analysis using timed configuration graphs 2009 In: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. - Piscataway, N.J. : IEEE Press. - 9781424445028 ; , s. 108-117 Conference paper (peer-reviewed)abstract The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.
11.	Bengtsson, Jerker, et al. (author) Methodologies and tools for development of signal processing software on multicore platforms 2008 In: 2008 proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture. - Piscataway, N.J. : IEEE Computer Society. - 9781424428366 ; , s. 2- Conference paper (peer-reviewed)
12.	Bengtsson, Jerker (author) Models and Methods for Development of DSP Applications on Manycore Processors 2009 Doctoral thesis (other academic/artistic)abstract Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory manycore processors. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory manycores, with respect to given application constraints. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. Automated parallelization, optimisation and mapping to a manycore processor benefits from the use of a concurrent programming model as the starting point. Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. The programming model should also abstract away machine dependent hardware details. The analytical study of WCDMA baseband processing in radio base stations, presented in this thesis, suggests dataflow models as a good match to the characteristics of the application and as execution model abstracting computations on a manycore. Construction of portable tools further requires a manycore machine model and an intermediate representation. The models are needed in order to decouple algorithms, used to transform and map application software, from hardware. We propose a manycore machine model that captures common hardware resources, as well as resource dependent performance metrics for parallel computation and communication. Further, we have developed a multifunctional intermediate representation, which can be used as source for code generation and for dynamic execution analysis. Finally, we demonstrate how we can dynamically analyse execution using abstract interpretation on the intermediate representation. It is shown that the performance predictions can be used to accurately rank different mappings by best throughput or shortest end-to-end computation latency.
13.	Bengtsson, Lars, 1958-, et al. (author) A high-performance embedded massively parallel processing system 1994 In: Proceedings of the First International Conference on Massively Parallel Computing Systems (MPCS) The Challenges of General-Purpose and Special-Purpose Computing. - Piscataway, N.J. : IEEE. - 0818663227 - 9780818663222 ; , s. 201-206 Conference paper (peer-reviewed)abstract A need to apply the massively parallel computing paradigm in embedded real-time systems is foreseen. Such applications put new demands on massively parallel systems, different from those of general purpose computing. For example, time determinism is more important than maximal throughput, physical distribution is often required, size, power, and I/O are important, and interactive development tools are needed. The paper describes an architecture for high-performance, embedded, massively parallel processing, featuring a large number of nodes physically distributed over a large area. A typical node has thousands of processing elements (PEs) organized in SIMD mode and is the size of the palm of a hand, Intermodule communication over a scalable optical network is described. A combination of wavelength division multiplexing (WDM) and time division multiplexing (TDM) is used. © 1994 IEEE.
14.	Bengtsson, Lars, 1958-, et al. (author) A processor array module for distributed, massively parallel, embedded computing 1993 In: Microprocessing and Microprogramming. - Amsterdam : Elsevier. - 0165-6074. ; 38:1-5, s. 529-537 Journal article (peer-reviewed)abstract With the increased degree of miniaturization resulting from the use of modem VLSI technology and the high communication bandwidth available through optical connections, it is now possible to build massively parallel computers based on distributed modules which can be embedded in advanced industrial products. Examples of such future possibilities are ''action-oriented systems'', in which a network of highly parallel modules perform a multitude of tasks related to perception, cognition, and action. The paper discusses questions of architecture on the level of modules and inter-module communication and gives concrete architectural solutions which meet the demands of typical, advanced industrial real-time applications. The interface between the processors arrays and the all-optical communication network is described in some detail. Implementation issues specifically related to the demand for miniaturization are discussed.
15.	Bengtsson, Lars, 1958-, et al. (author) Brains for Autonomous Robots : Hardware and Surgery Tools 1994 In: Proceedings of PerAc '94. From Perception to Action. - Los Alamitos : IEEE. - 0818664827 - 9780818664823 ; , s. 436-439 Conference paper (peer-reviewed)abstract This paper presents a hardware architecture and a software tool needed for future autonomous robots. Specific attention is given to the execution of artificial neural networks and to the need for a good inspection and visualization tool when developing this kind of systems. Achievable performance using state-of-the-art technology is estimated and module miniaturization issues are discussed. © 1994 IEEE.
16.	Bengtsson, Lars, 1958-, et al. (author) REMAP massively parallel computer platform for neural computations 1997 In: Proceedings of the Third International Conference on Microelectronics for Neural Networks (MicroNeuro’93). ; , s. 47-62 Conference paper (peer-reviewed)abstract The REMAP project addresses questions related to the use of massively parallel, distributed computing in embedded systems. Of specific interest is the execution of artificial neural network algorithms on multiple, cooperating processor arrays. This paper concentrates on the recently finished, and currently used, processor array prototype, REMAP-β, of SIMD (Single Instruction stream, Multiple Data streams) type. The architecture and implementation of the computer is described, both its overall structure and its constituent parts. Following this comes a discussion of its use as an architecture laboratory, which stems from the fact that it is implemented using FPGA (Field Programmable Gate Array) circuits. As an architecture laboratory the prototype can be used to implement and evaluate, e.g., various Processing Element (PE) designs. A couple of examples of PE architectures, including one with floating-point support, are given. The mapping of important neural network algorithms on processor arrays of this kind is shown, and possible tuning of the architecture to meet specific processing demands is discussed. Performance figures are given as well as implications for future VLSI implementations of the array.
17.	Bengtsson, Lars, et al. (author) The REMAP Reconfigurable Architecture : a Retrospective 2006 In: FPGA Implementations of Neural Networks. - New York : Springer-Verlag New York. - 0387284850 ; , s. 325-360 Book chapter (peer-reviewed)abstract The goal of the REMAP project was to gain new knowledge about the design and use of massively parallel computer architectures in embedded real-time systems. In order to support adaptive and learning behavior in such systems, the efficient execution of Artificial Neural Network (ANN) algorithms on regular processor arrays was in focus. The REMAP-β parallel computer built in the project was designed with ANN computations as the main target application area. This chapter gives an overview of the computational requirements found in ANN algorithms in general and motivates the use of regular processor arrays for the efficient execution of such algorithms. REMAP-β was implemented using the FPGA circuits that were available around 1990. The architecture, following the SIMD principle (Single Instruction stream, Multiple Data streams), is described, as well as the mapping of some important and representative ANN algorithms. Implemented in FPGA, the system served as an architecture laboratory. Variations of the architecture are discussed, as well as scalability of fully synchronous SIMD architectures. The design principles of a VLSI-implemented successor of REMAP-β are described, and the paper is concluded with a discussion of how the more powerful FPGA circuits of today could be used in a similar architecture. © 2006 Springer.
18.	Bengtsson, Lars, 1958, et al. (author) The REMAP Reconfigurable Architecture: a Retrospective 2005 In: FPGA Implementations of Neural Networks. - 0387284850 Book chapter (other academic/artistic)
19.	Bengtsson, Niklas, 1980- (author) Essays in Development and Labor Economics 2009 Doctoral thesis (other academic/artistic)abstract This thesis consists of three self-contained essays. Essay I. This essay uses time-series of rainfall to estimate the response of body weight to transitory changes in household income in rural Tanzania. The response is positive on average, but is markedly higher among female children. For female children, a ten-percent increase in household income implies an increase in body weight by about 0.4 kilos. In contrast, the body weight of adolescents and young adults is virtually invariant to transitory income changes. Essay II. In this essay, the impact of a village-level assistance program run by the Evangelical Lutheran Church of Tanzania is estimated. We find that the program increased literacy by 15-20 percentage points and educational attainment by 10-15 percentage points, but only among Protestant children. Catholic children living in the same targeted villages were unaffected. The results support the concern that faith organizations might overstate their ability to aid households of different faith. Essay III. This essay exploits a rapid introduction of an unconditional cash grant (child support) in South Africa in order to estimate the marginal propensity to consume and earn out of a permanent change in unearned income. We find that the marginal propensity to earn is about -0.25 to -0.4. A very small fraction of the grant is saved. All in all, the marginal propensities estimated here are all similar to those reported in comparable papers using US data. However, they stand in contrast to some results on conditional cash transfers in other developing countries.
20.	Bilstrup, Urban, et al. (author) A fault tolerance test enabling QoS in a Bluetooth piconet 2004 Conference paper (pop. science, debate, etc.)abstract An important trend, in personal area networks, is that time critical application becomes more common, e.g., voice over IP, video phone calls, network games. This segment of applications demands for quality of service (QoS) guarantees, to provide the correct functionality. The Bluetooth standard provides an optional interface to support QoS guarantees, but the standard does not suggest any actual implementation. A wireless communication channel is stochastic by nature, providing QoS guarantees with this precondition make traditional deterministic real-time theory obsolete. In this paper a probabilistic fault tolerance test enabling quality of service guarantees in a Bluetooth piconet is given. The basic Bluetooth network architecture is based on a master-slave configuration, i.e., a point to point connection. More advanced network architectures are possible where up to eight Bluetooth equipped units can be active members of one network (piconet). Furthermore, several piconets can interconnect and form a so called scatternet.
21.	Bilstrup, Urban, et al. (author) Capacity limitations in wireless sensor networks 2003 In: ETFA 2003. - Piscataway, N.J. : IEEE. - 0780379373 ; , s. 529-536 Conference paper (peer-reviewed)abstract It is expected that wireless sensor network will be used in home automation and industrial manufacturing in the future. The main driving forces for wireless sensor networks are fault tolerance, energy gain and spatial capacity gain. Unfortunately, an often forgotten issue is the capacity limits that the network topology of a wireless sensor network represents. In this paper we identify gains, losses and limitations in a wireless sensor network, using a simplified theoretical network model. Especially, we want to point out the stringent capacity limitations that this simplified network model provide. Where a comparison between the locality of the performed information exchange and the average capacity available for each node is the main contribution.
22.	Bilstrup, Urban, 1971- (author) Design Space Exploration of Wireless Multihop Networks 2005 Licentiate thesis (other academic/artistic)abstract This thesis explores the feasible design space of wireless multihop networks and identifies fundamental design parameters. In the process of exploring it is important to ignore all details and instead take a holistic view. This means that all protocol details are overseen, all details of radio wave propagation models are overseen and the system is modelled strictly on an architectural level. From a theoretical information perspective, there is a limit to the capacity that a certain bandwidth and a certain signal-to-noise ratio at the receiver can provide. This limit is approximated as a volume in the time-frequency-space domain. A single transmission is represented as an occupied volume in this domain. A wireless multihop network covers a spatial area, and the question is how multiple numbers of transmission volumes can be fit into a given limited spatial area. This volume fitting should be done in order to maximize the overall performance or to trade available resources to favour a specific characteristic in the wireless multihop network. The volume model is used for the design space exploration of a wireless multihop network. It is argued that the fault tolerance and the energy gain achieved in a multihop topology are its strength as compared to a single-hop architecture. It is further shown that the energy gain is achieved at the expense of delay and a greater end-to-end error probability. This indicates that these parameters must be very carefully balanced in order to gain in the global overall performance perspective. It can further be concluded that the overall spatial capacity is increased as a result of the spatial channel reuse in a multihop topology. On the other hand, it is also shown that the multihop topology introduces a rather stringent geometrical capacity limitation when the number of nodes of a wireless multihop network is increased. The dynamics (e.g. node mobility, changing radio channels etc.) of a large scale wireless multihop network is also a limiting factor. The nodes’ mobility creates a knowledge horizon beyond which very little can be known about the present network topology.
23.	Bilstrup, Urban, 1971-, et al. (author) Knowledge Horizon - Dynamic limitations in a wireless ad hoc network 2003 In: SNCNW 2003 Swedish National Computer Networking Workshop 2003 on-line proceedings. ; , s. 1-3 Conference paper (peer-reviewed)abstract In this paper we investigate the impact of node mobility in a wireless ad hoc network (WAHN). Especially we investigate the possibility to provide guaranteed services in a WAHN, i.e., the network topology predictability. We combine link expiration time (LET) estimation with information propagation speed (IPS) in a time-space diagram and as result an operation area is revealed. The result gives that a WAHN, where the nodes are mobile, has a knowledge horizon (KH), the distance of which is dependent on the mobility of the nodes. Beyond the KH, knowledge about the network state is impossible to achieve. Thus, we can not predict long distance network topology state when the node mobility is high.
24.	Bilstrup, Urban, et al. (author) The next challenge for the communication society : co-operating embedded systems 2003 Conference paper (peer-reviewed)
25.	Bilstrup, Urban, et al. (author) The use of clustered wireless multihop networks in industrial settings 2007 In: ETFA 2007. - Piscataway, NJ : IEEE Press. - 9781424408252 ; , s. 211-218 Conference paper (peer-reviewed)abstract This paper suggests a cluster collision avoidance mechanism and a dual transceiver architecture to be used in a clustered wireless multihop network. These two contributions make the clustered wireless multihop network the preferred architecture for future industrial wireless networks. The wireless multihop cluster consists of one master and several slaves, where some of the slaves will act as gateways between different clusters. Frequency hopping spread spectrum is used on a cluster level and to avoid frequency collisions between clusters a "neighbor cluster collision avoidance mechanism" is proposed and evaluated through simulations. To break up the dependence between the clusters, introduced by the gateway nodes, each node is equipped with two transceivers. The paper is concluded with a suggestion to use a clustered wireless multihop network with orthogonal hopping sequences for an industrial setting.
26.	Bilstrup, Urban, et al. (author) Using Dual-Radio Nodes to Enable Quality of Service in a Clustered Wireless Mesh Network 2006 In: IEEE Conference on Emerging Technologies and Factory Automation, 2006. ETFA '06. - Piscataway, N.J. : IEEE Press. - 0780397584 ; , s. 54-61 Conference paper (peer-reviewed)abstract In this paper some well established wireless technologies are merged into a new concept solution for a future industrial wireless mesh network. The suggested clustered wireless mesh network can handle probabilistic quality of service guarantees and is based on a dual-radio node architecture using synchronized frequency hopping spread spectrum Bluetooth radios. The proposed architecture gives a heuristic solution to the inter-cluster scheduling problem of gateway nodes in clustered architectures and breaks up the dependence between the local medium access schedules of adjacent clusters. The dual-radio feature also enables higher network connectivity, implying, for example, that a higher link redundancy can be achieved.
27.	Björklund, Erik, et al. (author) Admission Troponin T and measurement of ST-segment resolution at 60 min improve early risk stratification in ST-elevation myocardial infarction 2004 In: Eur Heart J. - : Oxford University Press (OUP). - 0195-668X .- 1522-9645. ; 25:2, s. 113-20 Journal article (peer-reviewed)abstract AIMS: The prognostic value of admission troponin T (tnT) levels and the resolution of the ST-segment elevation in ST-elevation myocardial infarction (STEMI) is well established. However, the combination of these two early available markers for predicting risk has not been evaluated. METHODS AND RESULTS: We evaluated 516 patients with fibrinolytic treated STEMI from the ASSENT-2 and ASSENT-PLUS studies, which had both admission tnT and ST-monitoring available. We used a prospectively defined cut-off value of tnT of 0.1microg/l. For ST-segment resolution, a cut-off of 50% measured after 60min was used. Both a tnT >/=0.1microg/l (n=116) and ST-segment resolution <50% (n=301) were related to higher one-year mortality, 13% vs 4% (P<0.001) and 8.4% vs 2.8% (P=0.009), respectively. In a multivariate analysis ST-segment resolution was and tnT showed a strong trend to be independently related to mortality. The combination of both further improved risk stratification. The one-year mortality in the group with elevation of tnT and without ST-segment resolution compared to the group without tnT elevation and with ST-segment resolution was 18.2% vs 2.8% (P<0.001). CONCLUSIONS: Both tnT on admission and ST-segment resolution after 60min are strong predictors of one-year mortality. The combination of both gives additive early information about prognosis and further improves risk stratification.
28.	Björklund, Erik, et al. (author) Pre-hospital thrombolysis delivered by paramedics is associated with reduced time delay and mortality in ambulance-transported real-life patients with ST-elevation myocardial infarction 2006 In: European Heart Journal. - : Oxford University Press (OUP). - 0195-668X .- 1522-9645. ; 27:10, s. 1146-1152 Journal article (peer-reviewed)abstract AIMS: There are sparse data on the impact of pre-hospital thrombolysis (PHT) in real-life patients. We therefore evaluated treatment delays and outcome in a large cohort of ambulance-transported real-life patients with ST-elevation myocardial infarction (STEMI) according to PHT delivered by paramedics or in-hospital thrombolysis. METHODS AND RESULTS: Prospective cohort study used data from the Swedish Register of Cardiac intensive care on patients admitted to the coronary care units of 75 Swedish hospitals in 2001-2004. Ambulance-transported thrombolytic-treated patients younger than age 80 with a diagnosis of acute myocardial infarction were included. Patients with PHT (n=1690) were younger, had a lower prevalence of co-morbid conditions, fewer complications, and a higher ejection fraction (EF) than in-hospital-treated patients (n=3685). Median time from symptom onset to treatment was 113 min for PHT and 165 min for in-hospital thrombolysis. One-year mortality was 7.2 vs. 11.8% for PHT and in-hospital thrombolysis, respectively. In a multivariable analysis, after adjusting for baseline characteristics and rescue angioplasty, PHT was associated with lower 1-year mortality (odds ratio 0.71, 0.55-0.92, P=0.008). CONCLUSION: When compared with regular in-hospital thrombolysis, pre-hospital diagnosis and thrombolysis with trained paramedics in the ambulances are associated with reduced time to thrombolysis by almost 1 h and reduced adjusted 1-year mortality by 30% in real-life STEMI patients.
29.	Björklund, Erik, et al. (author) Prehospital diagnosis and start of treatment reduce time delay and mortality in real life patients with ST-elevation myocardial infarction Journal article (peer-reviewed)
30.	Björklund, Erik, et al. (author) Prehospital diagnosis and start of treatment reduces time delay and mortality in real-life patients with STEMI 2005 In: Journal of Electrocardiology. - : Elsevier BV. - 0022-0736 .- 1532-8430. ; 38:4 Suppl, s. 186- Journal article (other academic/artistic)
31.	Björkman, Tommy, et al. (author) Experiences of stigma among people with severe mental illness. Reliability, acceptability and construct validity of the Swedish versions of two stigma scales measuring devaluation/discrimination and rejection experiences 2007 In: Nordic Journal of Psychiatry. - : Informa UK Limited. - 1502-4725 .- 0803-9488. ; 61:5, s. 332-338 Journal article (peer-reviewed)abstract Stigma has been identified as one of the most important obstacles for a successful integration of people with mental illness into the society. Research about stigma has shown negative attitudes among the public towards people with mental illness. Studies so far have, however, put little emphasis on how these negative attitudes are perceived by the mentally ill persons. The aim of the present study was to investigate acceptability and internal consistency of the Swedish versions of two stigma scales, the Devaluation and Discrimination scale and the Rejection experiences scale. Forty individuals were subject to an interview, which also comprised assessments of needs for care, quality of life, therapeutic relationship and empowerment. The results showed that both the Devaluation and Discrimination scale and the Rejection experiences scale had a good internal consistency and acceptability. Stigma in terms of perceived devaluation and discrimination was found to be most markedly associated with empowerment and rejection experiences was found to be most associated with the number of previous psychiatric admissions. It is concluded that the Swedish versions of the Devaluation and Discrimination scale and the Rejection experiences scale may well be used in further studies of stigma among people with mental illness.
32.	Boström, Ola, 1963, et al. (author) A new neck injury criterion candidate-based on injury findings in the cervical spinal ganglia after experimental neck extension trauma 1996 In: PROCEEDINGS OF THE 1996 INTERNATIONAL IRCOBI CONFERENCE ON THE BIOMECHANICS OF IMPACT, SEPTEMBER 11-13, DUBLIN, IRELAND. ; , s. 123-136 Conference paper (peer-reviewed)abstract In this study a mathematical model, based on Navier Stokes equations, was developed and validated against experimental data. This model predicts the pressure changes in the spinal canal as a function of the volume change inside the canal during neck bending in the x-z (sagittal) plane. Another aim of the study was to investigate pressure phenomena and ganglion injuries at static neck extension loading and dynamic neck extension trauma with a head-restraint present. Experiments on pigs were conducted. Preliminary results indicate that ganglion injuries, as well as pressure transients inside the spinal canal, seem to correlate to the phase shift when the neck passes an s-shape (or maximal retraction) during the rearward motion of the head. That is, when the upper neck quickly changes from a flexion to an extension shape. Static loading of the neck resulted in no signs of injuries to the ganglia. A possible candidate for a neck injury criterion is presented, based on the relative acceleration between the top and the bottom of the cervical spine. A tolerance level based on the pig tests is also discussed.
33.	Boström, Ola, 1963, et al. (author) Prediction of neck injuries in rear impacts based on accident data and simulations 1997 In: PROCEEDINGS OF THE 1997 INTERNATIONAL IRCOBI CONFERENCE ON THE BIOMECHANICS OF IMPACT. ; , s. 251-264 Conference paper (peer-reviewed)abstract Whiplash associated disorders, occurring in car accidents, are an increasing problem worldwide. According to real-life data from police records, the struck car's velocity change (delta V) and occupant gender are two of the most important factors related to Abbreviated Injury Scale (AIS) 1 neck injuries. In this study, a new rear-impact ranking of cars based on 4432 police reported accidents is presented. The ranking concerns the relative neck injury risk and compensates for the influences of car weight and gender. Moreover, some important factors influencing the risk of AIS 1 neck injury are proposed. These include: the stiffness, damping and yielding characteristics of the seat back, the muscle response of the occupant, and the delta V of the struck car and acceleration pulse. Using a mathematical model it is shown that the influence from these factors can be explained by a recently proposed neck injury criterion (NIC). This criterion is based on the neck motion at the passage of full neck retraction. The NIC, based on a number of volunteer tests, is analysed and validated. The consequence of injury outcome of an observed overall seat back stiffening is also discussed. In conclusion, for delta V below 20 km/h, real-life data show that the geometry of the head restraint is of minor importance. A seat back with low yielding limit or soft performance may be preferable. Moreover, the new NIC seems to be a good predictor of real-life neck injuries.
34.	Burman, Pia, et al. (author) Deaths Among Adult Patients With Hypopituitarism: Hypocortisolism During Acute Stress, and De Novo Malignant Brain Tumors Contribute to an Increased Mortality 2013 In: Journal of Clinical Endocrinology & Metabolism. - : The Endocrine Society. - 0021-972X .- 1945-7197. ; 98:4, s. 1466-1475 Journal article (peer-reviewed)abstract Context: Patients with hypopituitarism have an increased standardized mortality rate. The basis for Objective: To investigate in detail the cause of death in a large cohort of patients with hypopituitarism Design and Methods: All-cause and cause-specific mortality in 1286 Swedish patients with Main Outcome Measures: Standardized mortality ratios (SMR) were calculated, with stratification for Results: An excess mortality was found, 120 deaths vs 84.3 expected, SMR 1.42 (95% confidence Conclusion: Two important causes of excess mortality were identified: first, adrenal crisis in response
35.	Cato, Jan-Christer, et al. (author) Allmänprevention - ett laboratorieexperiment. 1971 Reports (other academic/artistic)abstract This investigation consists in part of an inventory of available literature regarding "general prevention". And primarily desling with the elaboration and testing of an experimental design with the purpose of preparing empirical research on this special criminological field. The introduced research design can be included in the "small group research area". It is a simulated game-situation in which different experimental groups are exposed to varying degrees of risk (for discovery) and punishment at the breaking of game rules. The putcome of the preliminary experiment indicate that variation and interrelation between the two depending variables correlate with "rule-braking" which in turn can be considered as an inversion of the concept of "general prevention".
36.	Compiling Stream-Language Applications to a Reconfigurable Array Processor 2005 In: ERSA'05. - Las Vegas : CSREA Press. - 9781932415742 - 1932415742 ; , s. 274-275 Conference paper (peer-reviewed)
37.	Davis, Edward W., et al. (author) Issues and applications driving research in non-conforming massively parallel processors 1992 In: Proceedings, The New Frontiers. - : IEEE Communications Society. - 0818644109 ; , s. 68-78 Conference paper (peer-reviewed)
38.	den Hollander, Lianne, et al. (author) Skin lamellar bodies are not discrete vesicles but part of a tubuloreticular network 2016 In: Acta Dermato-Venereologica. - : Medical Journals Sweden AB. - 0001-5555 .- 1651-2057. ; 96:3, s. 303-309 Journal article (peer-reviewed)
39.	Eriksson, Jan R, 1947-, et al. (author) Implementering av SAMLIC : förslaget och processen 2006 Reports (other academic/artistic)abstract Growing cities are increasing the demand for goods carrying traffic to function well with other traffic. The number of zones for unloading goods in the centre of Linköping is small compared to the number of delivery addresses and the number of goods distributors. The attendant phenomena are congestion and costs of congestion. Therefore the local network for freight forwarders in Linköping has taken the initiative to the SAMLIC project. SAMLIC stands for Coordinated Retail Distribution in Linköping City. Economic profitability is important to accomplish for a system with a joint venture in coordinated distribution to be successful. No matter which form the coordinated distribution takes, the savings for the freight forwarders must be of such a dimension that they find it profitable to join instead of delivering the goods by themselves. The aim of SAMLIC is to create an economically and logistically efficient system for goods distribution that is persistent and friendly to the environment. The aim of this implementation project is to make a proposal for an implementation of a functional system for coordinated retail distribution in the centre of Linköping. Also the process behind the proposal and the process of trying to implement the proposal will be described in the report. During a trial period of nine weeks in the spring of 2004 there was a coordinated distribution to the centre of Linköping. Three freight forwarders took part in this project. The experience of the trial shows that the needed number of trucks decreased by 25-35%, the total time for the distribution decreased by 15-20% and the total driving kilometer in the centre decreased by at least 50%. The coordinated distribution system might get introduced in several middle size and big cities. To efficiently handle this, there is a need of a common concept. In this project a concept of this type is developed as a prototype to be used at the implementation. The concept implies uniformity and clearness for freight forwarders and makes local solutions possible to be applied in different cities. The proposal is detailed enough to be a foundation of a decision between the freight forwarders to implement the coordinated distribution system. Besides, we show that the system is economically profitable and technically feasible. We include suggestions for texts for different necessary written agreements. Finally, why we did not succeed to implement the coordinated distribution system during the planned time for the project has different explanations. We will examine them in the report, too.
40.	Essayas, Gebrewahid, 1984-, et al. (author) Realizing Efficient Execution of Dataflow Actors on Manycores 2014 In: 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC 2014). - Los Alamitos, CA : IEEE Computer Society. ; , s. 321-328, s. 321-328 Conference paper (peer-reviewed)abstract Embedded DSP computing is currently shifting towards manycore architectures in order to cope with the ever growing computational demands. Actor based dataflow languages are being considered as a programming model. In this paper we present a code generator for CAL, one such dataflow language. We propose to use a compilation tool with two intermediate representations. We start from a machine model of the actors that provides an ordering for testing of conditions and firing of actions. We then generate an Action Execution Intermediate Representation that is closer to a sequential imperative language like C and Java. We describe our two intermediate representations and show the feasibility and portability of our approach by compiling a CAL implementation of the Two-Dimensional Inverse Discrete Cosine Transform on a general purpose processor, on the Epiphany manycore architecture and on the Ambric massively parallel processor array.
41.	Forsberg, Håkan, et al. (author) A scalable and pipelined embedded signal processing system using optical hypercube interconnects 2000 In: Proceedings of the 12th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2000), Las Vegas, NV, USA, Nov. 6-9, 2000. - Las Vegas : IASTED. ; , s. 265-272 Conference paper (peer-reviewed)abstract In this paper, we propose a system suitable for embedded signal processing with extreme performance demands. The system consists of several computational modules that work independently and send data simultaneously in order to achieve high throughput. Each computational module is composed of multiple processors connected in a hypercube topology to meet scalability and high bisection bandwidth requirements. Free-space optical interconnects and planar packaging technology make it possible to transform the hypercubes into planes and to take advantage of many optical properties. For instance, optical fan-out reduces hardware cost. This, altogether, makes the system capable of meeting high performance demands in, e.g., massively parallel signal processing. An example system with eleven computational modules and an overall peak performance greater than 2.8 TFLOPS is presented. The effective inter-module bandwidth in this configuration is 1,024 Gbit/s.
42.	Forsberg, Håkan, et al. (author) Embedded Signal Processing Using Free-Space Optical Hypercube Interconnects 2003 In: Optical Networks Magazine. - : Springer-Verlag. - 1572-8161 .- 1388-6916. ; 4:4, s. 35-49 Journal article (peer-reviewed)abstract The speed and complexity of integrated circuits are increasing rapidly. For instance, today's mainstream processors have already surpassed gigahertz global clock frequencies on-chip. As a consequence, many algorithms proposed for applications in embedded signal-processing (ESP) systems, e.g. radar and sonar systems, can be implemented with a reasonable number (less than 1000) of processors, at least in terms of computational power. An extreme inter-processor network is required, however, to completely implement those algorithms. The demands are such that completely new interconnection architectures must be considered.In the search for new architectures, developers of parallel computer systems can actually take advantage of optical interconnects. The main reason for introducing optics from a system point of view is the strength in using benefits that enable new architecture concepts, e.g. free-space propagation and easy fan-out, together with benefits that can actually be exploited by simply replacing the electrical links with optical ones without changing the architecture, e.g. high bandwidth and complete galvanic isolation.In this paper, we propose a system suitable for embedded signal processing with extreme performance demands. The system consists of several computational modules that work independently and send data simultaneously in order to achieve high throughput. Each computational module is composed of multiple processors connected in a hypercube topology to meet scalability and high bisection bandwidth requirements. Free-space optical interconnects and planar packaging technology make it possible to arrange the hypercubes as planes with an associated three-dimensional communications space and to take advantage of many optical properties. For instance, optical fan-out reduces hardware cost. Altogether, this makes the system capable of meeting high performance demands in, for example, massively parallel signal processing. One 64-channel airborne radar system with nine computational modules and a sustained computational speed of more than 1.6 Tera floating point operations per second (TFLOPS) is presented. The effective inter-module bandwidth in this configuration is 1 024 Gbit/s.
43.	Forsberg, Håkan, et al. (author) Key Issues in Implementing an Optoelectronic Planar Free-space Architecture for Signal Processing Applications 2003 In: IASTED International Multi-Conference on Applied Informatics. - : IASTED/ACTA Press. - 0889863415 ; , s. 621-629 Conference paper (pop. science, debate, etc.)abstract In this paper, we deal with the key issues in implementing an optoelectronic architecture suitable for embedded signal processing. The architecture is based on a system concept where free-space optical interconnects and planar packaging technologies make it possible to merge complicated and new parallel computer architectures into planes and to take advantage of many properties of optics. For instance, optical fan-out reduces the hardware cost as well as the all-to-all broadcast time. It is also possible to meet scalability and high bisection bandwidth requirements. The main results show that it is possible to build a 6D hypercube using planar optical substrates.
44.	Forsberg, Håkan, 1969-, et al. (author) Opportunities for Optical Planar Interconnection Technology in Terabit Switches 2003 In: Proceedings of the IASTED International Conference on Wireless and Optical Communications, July 2-4, 2003, Banff, Canada. - Anaheim; Calgary : ACTA Press. - 0889863741 - 9780889863743 ; , s. 155-164 Conference paper (peer-reviewed)abstract To keep up with the explosive growth of world-wide network traffic, large-capacity switches, with switching capacities in excess of several terabits per second, are becoming an essential part of the future. To realize such switches, new architecture concepts must be considered. In this paper, we discuss a technology for terabit switches that combines the advantage of using optical communication in all three spatial dimensions and the benefits of using surface mounted optoelectronic as well as electronic chips. We present three different types of packet-based switch fabrics, all based on the optical planar interconnection technology. We then discuss these in terms of capacity, scalability, and physical size. All three implementations have a single switch plane cross sectional bandwidth exceeding 5 Tbps.
45.	Forsberg, Håkan, et al. (author) Optical interconnect architectures in signal processing systems and terabit communication equipment 2001 In: Optik i Sverige 2001. - Stockholm : Swedish Optical Society. - 9172831936 Conference paper (peer-reviewed)abstract N/A
46.	Forsberg, Håkan, et al. (author) Radar signal processing using pipelined optical hypercube interconnects 2001 In: Proceedings of the 15th International Parallel and Distributed Processing Symposium. - Los Alamitos, California : IEEE Computer Society Press. - 0769509908 ; , s. 2043-2052 Conference paper (peer-reviewed)abstract In this paper, we consider the mapping of two radar algorithms on a new scalable hardware architecture. The architecture consists of several computational modules that work independently and send data simultaneously in order to achieve high throughput. Each computational module is composed of multiple processors connected in a hypercube topology to meet scalability and high bisection bandwidth requirements. Free-space optical interconnects and planar packaging technology make it possible to transform the hypercubes into planes. Optical fan-out reduces the number of optical transmitters and thus the hardware cost. Two example systems are analyzed and mapped onto the architecture. One 64-channel airborne radar system with a sustained computational load of more than 1.6 TFLOPS, and one ground-based 128-channel radar system with extreme inter-processor communication demands.
47.	Gebrewahid, Essayas, 1984- (author) Compiling Concurrent Programs for Manycores 2015 Licentiate thesis (other academic/artistic)abstract The arrival of manycore systems enforces new approaches for developing applications in order to exploit the available hardware resources. Developing applications for manycores requires programmers to partition the application into subtasks, consider the dependence between the subtasks, understand the underlying hardware and select an appropriate programming model. This is complex, time-consuming and prone to error.In this thesis, we identify and implement abstraction layers in compilation tools to decrease the burden of the programmer, increase programming productivity and program portability for manycores and to analyze their impact on performance and efficiency. We present compilation frameworks for two concurrent programming languages, occam-pi and CAL Actor Language, and demonstrate the applicability of the approach with application case-studies targeting these different manycore architectures: STHorm, Epiphany and Ambric.For occam-pi, we have extended the Tock compiler and added a backend for STHorm. We evaluate the approach using a fault tolerance model for a four stage 1D-DCT algorithm implemented by using occam-pi’s constructs for dynamic reconfiguration, and the FAST corner detection algorithm which demonstrates the suitability of occam-pi and the compilation framework for data-intensive applications. We also present a new CAL compilation framework which has a front end, two intermediate representations and three backends: for a uniprocessor, Epiphany, and Ambric. We show the feasibility of our approach by compiling a CAL implementation of the 2D-IDCT for the three backends. We also present an evaluation and optimization of code generation for Epiphany by comparing the code generated from CAL with a hand-written C code implementation of 2D-IDCT.
48.	Gebrewahid, Essayas, et al. (author) Mapping Occam-pi programs to a Manycore Architecture 2011 Conference paper (peer-reviewed)abstract Efficient utilization of available resources is a key concept in embedded systems. This paper is focused on providing the support for managing dynamic reconfiguration of computing resources in the programming model. We present an approach to map occam-pi programs to a manycore architecture, Platform 2012 (P2012). We describe the techniques used to translate the salient features of the occam-pi language to the native programing model of the P2012 architecture. We present the initial results from a case study of matrix multiplication. Our results show the simplicity of occam-pi program by 6 times reduction in lines-of-code.
49.	Gebrewahid, Essayas, 1984-, et al. (author) Programming Real-time Image Processing for Manycores in a High-level Language 2013 In: Advanced Parallel Processing Technology. - Berlin Heidelberg : Springer Berlin/Heidelberg. - 9783642452925 ; , s. 381-395 Conference paper (peer-reviewed)abstract Manycore architectures are gaining attention as a means to meet the performance and power demands of high-performance embedded systems. However, their widespread adoption is sometimes constrained by the need formastering proprietary programming languages that are low-level and hinder portability. We propose the use of the concurrent programming language occam-pi as a high-level language for programming an emerging class of manycore architectures. We show how to map occam-pi programs to the manycore architecture Platform 2012 (P2012). We describe the techniques used to translate the salient features of the language to the native programming model of the P2012. We present the results from a case study on a representative algorithm in the domain of real-time image processing: a complex algorithm for corner detectioncalled Features from Accelerated Segment Test (FAST). Our results show that the occam-pi program is much shorter, is easier to adapt and has a competitive performance when compared to versions programmed in the native programming model of P2012 and in OpenCL.
50.	Gebrewahid, Essayas, 1984- (author) Tools to Compile Dataflow Programs for Manycores 2017 Doctoral thesis (other academic/artistic)abstract The arrival of manycore systems enforces new approaches for developing applications in order to exploit the available hardware resources. Developing applications for manycores requires programmers to partition the application into subtasks, consider the dependence between the subtasks, understand the underlying hardware and select an appropriate programming model. This is complex, time-consuming and prone to error. In this thesis, we identify and implement abstraction layers in compilation tools to decrease the burden of the programmer, increase program portability and scalability, and increase retargetability of the compilation framework. We present compilation frameworks for two concurrent programming languages, occam-pi and CAL Actor Language, and demonstrate the applicability of the approach with application case-studies targeting these different manycore architectures: STHorm, Epiphany, Ambric, EIT, and ePUMA. For occam-pi, we have extended the Tock compiler and added a backend for STHorm. We evaluate the approach using a fault tolerance model for a four stage 1D-DCT algorithm implemented by using occam-pi's constructs for dynamic reconguration, and the FAST corner detection algorithm which demonstrates the suitability of occam-pi and the compilation framework for data-intensive applications. For CAL, we have developed a new compilation framework, namely Cal2Many. The Cal2Many framework has a front end, two intermediate representations and four backends: for a uniprocessor, Epiphany, Ambric, and a backend for SIMD based architectures. Also, we have identied and implemented of CAL actor fusion and fission methodologies for efficient mapping CAL applications. We have used QRD, FAST corner detection, 2D-IDCT, and MPEG applications to evaluate our compilation process and to analyze the limitations of the hardware.

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