| 1. |
- Abdulaziz, Mohammed, 1983, et al.
(författare)
-
A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS
- 2019
-
Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 67:4, s. 1588-1600
-
Tidskriftsartikel (refereegranskat)abstract
- © 2019 IEEE. This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm 2 . The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between-93 and-96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of-245 dB. The lock time in low-noise mode is up to 12μs, which is improved to 3μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between-235 and-240 dB.
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| 2. |
- Abdulaziz, Mohammed, et al.
(författare)
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A 3.4mW 65nm CMOS 5th Order Programmable Active-RC Channel Select Filter for LTE Receivers
- 2013
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Ingår i: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013. - 1529-2517. - 9781467360593 ; , s. 217-220
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Konferensbidrag (refereegranskat)abstract
- In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm CMOS technology with a core area of 0.29mm2. Its total current consumption is 2.83mA from a 1.2V supply. The measured input referred noise is 39nV/ √ Hz, the in-band IIP3 is 21.5dBm, at the band-edge the IIP3 is 20.7dBm, the out-of-band IIP3 is 20.6dBm, and the compression point is 0dBm.
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| 3. |
- Abdulaziz, Mohammed, et al.
(författare)
-
A 4th Order Gm-C Filter with 10MHz Bandwidth and 39dBm IIP3 in 65nm CMOS
- 2014
-
Ingår i: [Host publication title missing]. - 1930-8833. ; , s. 367-370
-
Konferensbidrag (refereegranskat)abstract
- Gm-C filters suffer from limited dynamic range due to a trade-off between noise and linearity in OTA design. This paper therefore presents a filter with a linearization technique to break this trade-off. This technique is demonstrated by a low power 4th order 10MHz Butterworth Gm-C low pass filter. The filter was implemented in 65nm CMOS technology with a core area of 0.19mm2 and a total current consumption of 3.5mA from a 1.2V supply. The measured input referred noise is 31nV/√Hz, the maximum in-band IIP3 is 39dBm, the out-of-band IIP3 is 34dBm, and the compression point is 8.2dBm.
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| 4. |
- Abdulaziz, Mohammed, et al.
(författare)
-
A Cellular Receiver Front-End with Blocker Sensing
- 2016
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Ingår i: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016. - 9781467386517
-
Konferensbidrag (refereegranskat)abstract
- A receiver front-end supporting contiguous and non-contiguous intra-band carrier aggregation scenarios with a fully integrated spectrum sensor that can detect both in-gap and out-of-band blockers has been implemented in 65nm CMOS technology. An NF of 2.5dB is achieved using a noise canceling LNTA, and linearized OTAs are used to achieve an IIP3 improvement of up to 6.5dB in-band and 11dB at the filter band edge. The spectrum sensor can detect blocker levels in 22 steps of 9MHz between -100MHz and 100MHz IF. The system consumes between 36.6mA and 57.6mA from a 1.2V supply.
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| 5. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Compensation Technique for Two-Stage Differential OTAs
- 2014
-
Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 61:8, s. 594-598
-
Tidskriftsartikel (refereegranskat)abstract
- In this paper a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole.The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values which makes it attractive for low power applications with low area overhead.
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| 6. |
- Abdulaziz, Mohammed, et al.
(författare)
-
A Linearization Technique for Differential OTAs
- 2017
-
Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 64:9, s. 1002-1006
-
Tidskriftsartikel (refereegranskat)abstract
- This brief presents an operational transconductance amplifier (OTA) linearization technique that is applied to a low-noise amplifier (LNA) and an OTA-C filter. Simulations show the effectiveness of the proposed technique on the LNA, whose noise and gain performance remain unaffected while the linearity is significantly improved. Measurements of the 80-MHz fourth order Butterworth OTA-C filter are also presented. It is implemented using six OTAs instead of eight, thus reducing the power consumption and area. The filter is implemented in 65-nm low-power CMOS, with a core area of 0.05 mm 2 and consumes 12.6 mA from 1.2 V supply. The measured in-band noise voltage is below 42 nV/ Hz‾‾‾√ , and the measured third order intercept point improvement using OTA linearization is up to 17 dB in-band and about 3 dB out-of-band. Supply and temperature variation measurements on three samples show that the linearization is effective without a need for bias adjustment.
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| 7. |
- Ahmad, Waqas, et al.
(författare)
-
A Fully Integrated 26dBm Linearized RF Power Amplifier in 65nm CMOS Technology
- 2015
-
Konferensbidrag (refereegranskat)abstract
- In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 dBm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 dB, and the output referred 1-dB compression point is 25.4 dBm. The ACLR1 (5 MHz offset) is better than -33 dBc while transmitting a 23dBm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm 2 of chip area.
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| 8. |
- Ahmad, Waqas, et al.
(författare)
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A Fully Integrated Radio-Fiber Interface in 65 nm CMOS Technology
- 2014
-
Ingår i: IEEE Photonics Technology Letters. - 1041-1135. ; 26:5, s. 444-446
-
Tidskriftsartikel (refereegranskat)abstract
- In this work we present a fully integrated Radio-Fiber interface implemented in 65nm CMOS, intended for remote antenna units (RAUs) in distributed antenna systems. To relax the requirements on the optical components, an intermediate frequency (IF) signal (100MHz) is transmitted over the multi-mode fiber, which is then up-converted to 2.2GHz inside the RAU. Local Oscillator (LO) signals to the mixers are generated by an on-chip frequency synthesizer. The measured optical to electrical conversion gain\,(V/W) is 59\,dB, whereas the input referred current noise is 3.5pA/$\sqrt{\mathrm{Hz}}$ and SFDR is 96.5dBHz^2/3. An LO leakage of -40dBc and an image rejection ratio of 43\,dB is measured. The circuit achieves an adjacent channel leakage ratio (ACLR) of -39dB and -41dB, for a 10MHz 32QAM signal at output power of 1dBm, and a 3.84MHz QPSK signal at 4dBm, respectively.
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| 9. |
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| 10. |
- Ahmad, Waqas, et al.
(författare)
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CMOS Adaptive TIA with Embedded Single-Ended to Differential Conversion for Analog Optical Links
- 2015
-
Ingår i: 2015 IEEE International Symposium on Circuits and Systems (ISCAS). - 9781479983919
-
Konferensbidrag (refereegranskat)abstract
- A variable gain transimpedance amplifier (TIA) is presented featuring single-ended to differential conversion by means of negative feedback. The proposed topology also ensures stability when amplifier gain is varied. Furthermore, effective input capacitance of the TIA is reduced by using a positive capacitive feedback. The circuit is intended for intermediate frequency (IF) over fiber systems, but can be readily adapted for other applications. When simulated with a photodiode capacitance of 1.4 pF, the TIA exhibits a tunable gain range of 51 to 73dBΩ with a bandwidth of 550 MHz. The circuit designed in a standard 65nm CMOS process consuming 4mA from a 1.2V supply, achieves a spurious free dynamic range (SFDR) of 109dB·Hz 2/3 at 100 MHz.
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| 11. |
- Ahmad, Waqas, et al.
(författare)
-
CMOS Integrated Remote Antenna Unit for Fiber-Fed Distributed MIMO Systems
- 2017
-
Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480. ; 65:1, s. 173-186
-
Tidskriftsartikel (refereegranskat)abstract
- A fully integrated remote antenna unit (RAU) intended for fiber-fed distributed multiple-input multiple-output systems is presented. The circuit is designed for narrowband (60 MHz) time-division duplex systems, where an IF over fiber approach is chosen to facilitate the use of low-cost optical components and integrated photodetectors. A novel antenna switch control scheme is introduced, which enables the use of an integrated antenna switch instead of a bulky off chip circulator. The reference frequency signal is distributed in the fiber together with user data and used by a phase-locked-loop-based frequency synthesizer to generate the local oscillator signal inside the RAU, hence synchronizing all RAUs of the distributed antenna system. At an operating frequency of 2.1 GHz, the measured optical-to-electrical conversion gain of the downlink is 71.7 dB, the error vector magnitude is 3.2%, and the adjacent channel leakage ratio is 39.2 dBc at an output power of +3 dBm for a 16-quadrature amplitude modulation (16-QAM) long-term evolution downlink signal. The uplink has a gain of 32.5 dB, a noise figure of 3.5 dB, and an in-band third-order intercept point of -12 dBm. Implemented in a standard 65-nm CMOS process, the complete RAU occupies just 2 mm2 of die area and consumes 146 mW during downlink signal transmission and 122 mW during uplink signal reception.
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| 12. |
- Ahmad, Waqas, et al.
(författare)
-
Fully Integrated Radio over Fiber Downlink for Distributed Multi-antenna Systems in 65nm CMOS
- 2014
-
Ingår i: 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS). - 9781479978694 ; , s. 353-356
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a fully integrated downlink for low-cost remote antenna units in fiber-fed distributed multi-antenna systems. To reduce the cost of optical parts, an intermediate frequency(IF) signal is distributed over the fiber, and the circuit consists of an optical receiver, a single side-band frequency up-converting radio transmitter, and LO generation circuitry. The optical to electrical conversion gain(V/W) of the system is 59dB, and an output referred 1dB compression point of +6dBm and an OIP3 of +17dBm are measured. The SFDR of the circuit is 96.5 dBHz^2/3. The phase noise of the PLL measured at 4.2GHz is -145dBc/Hz at 20MHz offset, where as the reference spur level is -58dBc. The circuit is fabricated in a standard 65nm CMOS process and occupies just 0.8mm^2 of chip area including bond pads.
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| 13. |
- Ahmad, Waqas, et al.
(författare)
-
Performance evaluation of N-well/P-sub photodiodes in 65nm CMOS process
- 2013
-
Ingår i: [Host publication title missing]. - 9781479904648 ; , s. 135-136
-
Konferensbidrag (refereegranskat)abstract
- This work explores the n-well/p-substrate photodiode in a deep submicron CMOS process. A CMOS chip is designed featuring different structures of the photodiode. When characterized at a wavelength of 850nm DC responsivities between 0.12 and 0.16 A/W and 3-dB bandwidths of about 6 MHz with a roll-off of about 5.5dB/decade are measured. These investigations are very useful in designing the transimpedance amplifier and equalizer for a fully integrated optical receiver. According to the authors’ knowledge it is the first reported study on n-well/p-sub photodiodes in a 65nm CMOS technology.
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| 14. |
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| 15. |
- Andersson Hägglund, Douglas, et al.
(författare)
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Analog Integrated Audio Frequency Synthesizer
- 2016
-
Ingår i: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. - 9781509015702 ; , s. 83-86
-
Konferensbidrag (refereegranskat)abstract
- In this paper we present an audio synthesizer that creates audio signals, intended to be reproduced as sound by a loudspeaker. This paper details the design, implementation and verification of an analog, subtractive audio synthesizer. The synthesizer produces a variety of waveforms spanning approximately 3 octaves. The frequency is controlled by an external voltage and the harmonic content is regulated by a tunable filter. The system is fabricated in 130 nm CMOS. Current consumption measures between 1.8 and 2.1 mA from a supply of 1.2 V.
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| 16. |
- Bondarik, Alexander, et al.
(författare)
-
Microstrip antenna array integrated with 60 GHz band CMOS injection locked power amplifier
- 2016
-
Ingår i: 2016 10th European Conference on Antennas and Propagation, EuCAP 2016. - 9788890701863
-
Konferensbidrag (refereegranskat)abstract
- A microstrip antenna integration with a power amplifier is presented for the 60 GHz band. The antenna is a single layer 4×4 square patches array. The power amplifier is injection locked, designed in a 65 nm CMOS technology, with single-ended input and output signals. The integration is realized by means of bond wire connections. The antenna and the power amplifier are fabricated, characterized and measured separately. The integrated design is fabricated and measured, results are de-embedded to extract the power amplifier parameters and to compare with separate device measurements. At 56.5 GHz the integrated sample has about 12 dB gain increase with respect to the antenna sample without power amplifier. The presented design is targeting 60 GHz band wireless communication system applications.
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| 17. |
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| 18. |
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| 19. |
- Felding, Henrik, et al.
(författare)
-
A three bit second order audio band delta sigma modulator with 98.2dB SQNR
- 2016
-
Ingår i: 2016 International Symposium on Integrated Circuits, ISIC 2016. - 9781467390194
-
Konferensbidrag (refereegranskat)abstract
- A three bit second order delta sigma modulator for audio applications implemented in 130nm CMOS technology is presented. The modulator features two integrators, a flash quantizer and two current steering DACs. In order to minimize the effect of delays in the DACs, excessive loop delay (ELD) compensation is utilized. Using an oversampling ratio (OSR) of 80, the design consumes 2.8mW and achieves a simulated signal to quantization noise ratio (SQNR) of 98.2dB. The chip area is minimized by decreasing the number of digital to analog converters (DACs) by using the concept of partial integration. The compact design occupies an active core area of 630μm × 600μm.
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| 20. |
- Forsberg, Therese, et al.
(författare)
-
A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS
- 2018
-
Ingår i: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). - 9781538676578 - 9781538676561
-
Konferensbidrag (refereegranskat)abstract
- A mm-wave divide-by-two circuit with high injection efficiency, implemented in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process is demonstrated stand-alone, as well as using an on-chip voltage controlled oscillator (VCO) as the input signal source. Measurements show that the divider has a 30.1 % tuning range centered at an output frequency of 24 GHz, at an input signal power of -1.5 dBm, and a power consumption of 4.3 mW from a 0.9 V supply. The VCO and divider combination has a tuning range of 10.2 %, centered at an output frequency of 30.2 GHz, at a total power consumption of 6.3 mW, and an output phase noise of -111 dBc/Hz at 10 MHz offset. The active area of the divider is 0.032 mm 2 and of the divider and VCO combination 0.043 mm 2 .
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| 21. |
- Forsberg, Therese, et al.
(författare)
-
A 65 nm CMOS varactorless mm-wave VCO
- 2014
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Ingår i: Proc. IEEE International Symposium on Integrated Circuits 2014.
-
Konferensbidrag (refereegranskat)
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| 22. |
- Forsberg, Therese, et al.
(författare)
-
A two-stage mm-wave PA with 18.5% PAE in 65 nm CMOS
- 2015
-
Ingår i: 2015 Asia-Pacific Microwave Conference (APMC). - 9781479987658 ; 1, s. 1-3
-
Konferensbidrag (refereegranskat)abstract
- A two-stage mm-wave power amplifier (PA) is presented. Designed in a 65 nm CMOS process, the PA employs capacitive neutralization in each stage for increased differential isolation and gain. Baluns are used for single-ended input/output signal to balanced signal conversion, and the interstage matching consists of a 2:1 transformer. With a 1.2 V supply, at 67 GHz, measurements show a gain of 16.8 dB, a 1dB-compression point (P1dB) of 8.4 dBm and a saturated output power (Psat) of 11.8dBm, with a peak power added efficiency (PAE) of 18.5 %. The PA core occupies an area of 100 um x 300 um.
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| 23. |
- Forsberg, Therese, et al.
(författare)
-
Two mm-Wave VCOs in 28-nm UTBB FD-SOI CMOS
- 2017
-
Ingår i: IEEE Microwave and Wireless Components Letters. - 1531-1309. ; 27:5, s. 509-511
-
Tidskriftsartikel (refereegranskat)abstract
- Two 60-GHz band voltage controlled oscillators (VCOs) designed in a 28-nm ultrathin body and buried oxide fully depleted silicon on insulator (UTBB FD-SOI) CMOS process are demonstrated and compared. Both VCOs have identical cross-coupled nMOS cores and dissipate 3.15 mW from a 0.9-V supply. The first design uses a standard FET current source and achieves a figure of merit (FOM) of −181 dBc/Hz, whereas the second employs a filtered current source and achieves a state-of-the-art FOM of −187 dBc/Hz. The achieved 6-dB improvement demonstrates the efficiency of the filtering technique at millimeter wave frequencies and the feasibility of efficient low-phase noise designs in 28-nm UTBB FD-SOI CMOS. The active area of the filtered VCO is 90μm×180μm and the standard VCO has an area of 80μm×110μm.
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| 24. |
- Forsberg, Therese, et al.
(författare)
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Two Ultra-Low Power MM-Wave Push-Pull VCOs in FD-SOI CMOS
- 2018
-
Ingår i: Proceedings of 2018 Asia-Pacific Microwave Conference. - 9784902339451 - 9781538621844 ; , s. 1130-1132
-
Konferensbidrag (refereegranskat)abstract
- Two low-power mm-wave voltage controlled oscillators (VCOs) designed in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process are demonstrated, using a push-pull differential architecture. Measurement show that the first VCO has a 10.8% tuning rage centered at 30.3 GHz, and the second has a 8.9 % tuning range at 58.7 GHz. The 30 GHz VCO consumes 1.06 mW from a 1 V supply, and has a -119 dBc/Hz phase noise at 10 MHz offset, achieving a figure of merit of -188.4 dB. The 60 GHz VCO consumes 1.35 mW and has a -111.9 dBc/Hz phase noise at 10 MHz offset, achieving a figure of merit of -186.2 dB. Their active areas are 0.03 mm 2 and 0.096 mm 2 respectively.
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| 25. |
- Ghotbi, Iman, et al.
(författare)
-
A 1.7-6.4 GHz fourth-order RF filter with 1-40% fractional bandwidth in 22-nm FDSOI
- 2022
-
Ingår i: 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC). - 9781665471442 - 9781665471435 ; , s. 1-3
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Konferensbidrag (refereegranskat)abstract
- The rise of 5G technology leads to a boom in the demand for widely available wireless connectivity while requiring telecommunication networks to improve spectral efficiency and deploy dynamic spectrum sharing (DSS) and carrier aggregation (CA). This imposes more stringent intermodulation test scenarios and blocking requirements on RF transceivers. In addition, they are required to be programmable for various bandwidth and gain configurations over a broad frequency range.
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| 26. |
- Ghotbi, Iman, et al.
(författare)
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A Reconfigurable RF Filter With 1%–40% Fractional Bandwidth for 5G FR1 Receivers
- 2023
-
Ingår i: IEEE Solid-State Circuits Letters. - 2573-9603. ; 6, s. 97-100
-
Tidskriftsartikel (refereegranskat)abstract
- This letter presents a radio frequency front-end (RFFE) for 5G new radio (NR) receivers operating in frequency range 1 (FR1). The core of this RFFE is a synthetic fourth-order Q -enhanced RF filter employing gm -boosting, noise-canceling, capacitive cross-coupling, and forward body-biasing techniques to achieve 1.7 to 6.4 GHz operating range and 1% to 40% adjustable fractional bandwidth (FBW). The function of the filter is based on subtracting out-of-phase signals in the passband and in-phase signals in the stopband. Two Q -enhanced LC resonators are utilized for outphasing. The filter is preceded by a low-noise transconductance amplifier, and it is followed by a programmable gain amplifier and a differential buffer stage for the measurement purposes and gain equalization. The experimental results demonstrate that the voltage gain is tunable between 18 and 47 dB with 0.2 dB steps, which leads to an equalized output power in all the filter configurations. Fabricated in 22 nm fully depleted silicon on insulator (FD-SOI) technology, the RFFE achieves 4.6-dB NF, −14 dBm IB-IIP3, and 26-dBm IB-IIP2 at 4 GHz. Notably, the fourth-order steep roll-off provides 22-dBm OOB-IIP3 at 2×BW frequency offset. The entire RFFE draws 22–45 mA from a 1-V supply and the filter core occupies 0.11 mm2 chip area.
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| 27. |
- Ghotbi, Iman, et al.
(författare)
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A reconfigurable RF front-end for 5G direct sampling receivers with an optimized calibration scheme
- 2024
-
Ingår i: AEÜ - International Journal of Electronics and Communications. - 1434-8411. ; 175
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a reconfigurable radio frequency front-end (RFFE) tailored for direct RF sampling receivers operating within Frequency Range 1 (FR-1) of the 5G spectrum. It consists of a balun-LNA, a noise-cancelling, current-reuse, Q-enhanced filter, and a programmable gain amplifier (PGA). Fabricated in 22-nm FD-SOI technology, the RFFE covers the entire frequency range from 1.7 to 6.4 GHz with a tunable bandwidth ranging from 50 MHz to 1.2 GHz. The experimental results confirm that the RFFE achieves 3.9 dB NF, 55 dB ultimate OOB rejection, −4 dBm IB-IIP3, and 23 dBm OOB-IIP3. Furthermore, a digital calibration scheme is proposed to compensate for process, voltage, and temperature (PVT) variations, achieving lower than 2 % error in 6.61 µs on average. Subsequently, a proximal policy optimization (PPO) agent is employed to choose the optimal policy for the successive adjustments of quality factors and resonance frequencies of the filter’s resonators. As a result, the proposed reinforcement learning algorithm reduces the calibration’s convergence time by 59 %.
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| 28. |
- Ghotbi, Iman, et al.
(författare)
-
A Wideband Balun-LNA for Sub-6-GHz 5G NR with Multi-Mode Operation in 22-nm FD-SOI
- 2022
-
Ingår i: 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS). - 9781665401067 - 9781665401050 ; , s. 94-98
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Konferensbidrag (refereegranskat)abstract
- A wideband balun-LNA featuring common gate (CG) – common source (CS) noise cancelling, current reuse, and g0.8 GHz to 7.3 GHz that fulfills the requirements of sub-6 GHzm -boosting is presented. It covers frequency range from 5G new radio (NR) technology. The LNA provides balanced output for identical differential loads and employs forward body biasing for linearity improvement. The LNA has low sensitivity to supply voltage variations due to its symmetrical complementary design and efficient biasing. The mode of operation can be adjusted between high-performance (HP) and high-tolerance (HT) modes by changing the ratio of the currents flowing through CG and CS branches. Post-layout simulations in 22 nm FDSOI technology yields a minimum noise figure of 2 dB in HP mode while IIP3 reaches -2.1 dBm inHT mode. The power consumption varies between 0.7 mW to 1.8 mW in different modes and the supply voltage is 0.85 V.
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| 29. |
- Ghotbi, Iman, et al.
(författare)
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Broadband RF Front-End Featuring a Reconfigurable Q-Enhanced Filter for Upper Mid-Band 6G Receivers
- 2023
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Ingår i: 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS). - 9798350300253 - 9798350300246 ; , s. 1-5
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Konferensbidrag (refereegranskat)abstract
- This paper presents a radio frequency front-end (RFFE) comprised of a cascode low-noise amplifier (LNA) and a reconfigurable Q-enhanced filter. Employing a dual-resonant input matching network, the LNA attains a significantly wide bandwidth. The filter consists of four Q-enhanced resonators enabling three modes of operation: 1) dual-band filter, 2) single band-pass filter (BPF) along with a tunable in-band (IB) notch, and 3) dual-band filter with extreme out-of-band (OOB) blocker rejection. The fractional bandwidth and center frequency are continuously tunable in the range of 1-12% and 7-20 GHz respectively. Designed and simulated in 22-nm FD-SOI technology, the RFFE achieves 33 dB gain, 4.4 dB NF, and −6.1 dBm IB-IIP3. Moreover, the RFFE can attenuate OOB and IB interferers by at least 50 dB and 56 dB respectively. The power consumption varies between 26 mW and 50 mW depending on the configuration, and the occupied active area is 0.19 mm^2 .
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| 30. |
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| 31. |
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| 32. |
- Lindstrand, Jonas, et al.
(författare)
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A 1.6-2.6GHz 29dBm Injection-Locked Power Amplifier with 64% peak PAE in 65nm CMOS
- 2011
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Ingår i: Proc. IEEE European Solid State Circuits Conference. - 1930-8833. ; , s. 299-302
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Konferensbidrag (refereegranskat)abstract
- This paper presents a wideband CMOS power amplifier intended for cellular handset applications. The circuit exploits injection locking to achieve a power gain of 20.5dB from a single stage amplifier. The maximum output power of 29dBm, with a peak drain- and power-added-efficiency (PAE) of 66% and 64%, respectively, occurs at a center frequency of 2GHz with a 3V supply. A cross-coupled cascode topology enables a wideband PAE exceeding 50% from 1.6 to 2.6GHz. For output power levels below 4dBm the circuit operates as a linear class AB amplifier with a power consumption of 17mW from a 0.48V supply. The power gain of 20.5dB is kept constant for all output powers; with an AM-AM- and AM-PM-conversion of 0.2dB and 17deg, respectively, over the entire WCDMA dynamic range of 80dB. The circuit is implemented in a standard 65nm CMOS process with a total chip area of 0.52x0.48mm2 including pads.
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| 33. |
- Lindstrand, Jonas, et al.
(författare)
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An Injection-Locked Power Up-Converter in 65-nm CMOS for Cellular Applications
- 2019
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480. ; 67:3, s. 1065-1077
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents an injection-locked 65-nm CMOS circuit that upconverts and power amplifies baseband signals to RF. The circuit delivers an RF output power of 28.7 dBm, with a power gain and maximum power added efficiency (PAE) of 20.6 dB and 68.1%, respectively. Both AM–AM-conversion and AM–PM-conversion are low, less than 1 dB and 1°, respectively, resulting in an EVM of 4.7% for Long Term Evolution (LTE) and 4.1% for WCDMA signals. The circuit provides an average output power of 20.3 dBm for LTE, with a PAE of 44.1%, andfor WCDMA, the average output power is 23.8 dBm with a PAE of 55.6%. Supply modulation improves power back-off efficiency and the voltage range is from 540 mV to 3 V. The spectral mask for LTE signals has a worst case ACLR of 33.2 dBc using predistortion. For WCDMA signals, ACLR1 is 39.9 dBc and ACLR2 is 47.2 dBc, both values worst case and using baseband predistortion. This performance is achieved by introducing a cross-coupled cascode topology, and supporting theory and simulations are presented. The startup loop-gain and smallsignal equivalents are derived, a power dissipation analysis is performed, and the injection circuit is analyzed to investigate the AM–PM behavior. Analysis and simulations show that, compared to conventional cascode amplifiers, PAE is improved by 24% (15% points). The circuit is implemented in an STM 65-nm CMOS process and occupies an area of 1.0 × 0.53 mm2.
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| 34. |
- Lindstrand, Jonas, et al.
(författare)
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Mixed-mode transmitter architectures
- 2011
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Ingår i: Proc. 2011 Swedish System-on-chip Conference. ; , s. 1-4
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)
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| 35. |
- Liu, Xiaodong, et al.
(författare)
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A 65 nm CMOS Wideband Radio Receiver with ΔΣ-Based A/D-Converting Channel-Select Filters
- 2016
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 51:7, s. 1566-1578
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a wideband quadrature radio receiver employing ΔΣ-based A/D-converting channel-select filters (ADCSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, where a first-order ΔΣ modulator is incorporated into a fourth-order Butterworth channel-select filter (CSF) to provide sufficient dynamic range for a cellular system. A design methodology for the ADCSF is derived, where the transfer function of the CSF is preserved. The 65 nm CMOS receiver has a frequency range of 0.6-3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.3 to 3.9 dB, with a current consumption in 2xLTE20 mode between 33 mA at 0.6 GHz and 44 mA at 3.0 GHz from a 1.2 V supply, including 10-21 mA for LO phase generation and distribution. The SNDR is 47-51 dB at an LO frequency of 1.8 GHz.
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| 36. |
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| 37. |
- Nejdel, Anders, et al.
(författare)
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A 0.7 - 3.7 GHz Six Phase Receiver Front-End With Third Order Harmonic Rejection
- 2013
-
Ingår i: IEEE.
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Konferensbidrag (refereegranskat)abstract
- This paper presents a highly linear receiver frontend operating from 700 MHz to 3.7 GHz with 3rd order harmonic rejection. It consists of a complementary low noise transconductance amplifier with capacitive cross coupling and negative gm current sources, a six phase current-mode passive mixer, and baseband transimpedance amplifiers providing programmable gain. The circuit has been fabricated in 65 nm CMOS technology with an active area of just 0.09 mm2. It consumes 7.2 mA, excluding the six phase local oscillator generation, from a 1.2 V supply, achieving a third order harmonic rejection of 40 dB, and a noise figure of 3 to 4.5 dB at 52 dB gain. The out of band IIP2 and IIP3 at full gain is +55 dBm and +5 dBm, respectively.
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| 38. |
- Nejdel, Anders, et al.
(författare)
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A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
- 2013
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 74:1, s. 47-57
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a wireless receiver frontend intended for cellular applications implemented in a 65 nm CMOS technology. The circuit features a low noise amplifier (LNA), quadrature passive mixers, and a frequency divider generating 25 % duty cycle quadrature local oscillator (LO) signals. A complementary common-gate LNA is used, and to meet the stringent linearity requirements it employs positive feedback with transistors biased in the sub-threshold region, resulting in cancellation of the third order non-linearity. The mixers are also linearized, using a baseband to LO bootstrap circuit. Measurements of the front-end show about 3.5 dB improvement in out-ofband IIP3 at optimum bias of the positive feedback devices in the LNA, resulting in an out-of-band IIP3 of 10 dBm. With a frequency range from 0.7 to 3 GHz the receiver front-end covers most important cellular bands, with an input return loss above 9 dB and a voltage gain exceeding 16 dB for all bias settings. The circuit consumes 4.38 mA from a 1.5 V supply.
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| 39. |
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| 40. |
- Nejdel, Anders, et al.
(författare)
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A Noise Cancelling 0.7-3.8 GHz Resistive Feedback Receiver Front-End in 65 nm CMOS
- 2014
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Ingår i: [Host publication title missing]. - 1529-2517. ; , s. 35-38
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Konferensbidrag (refereegranskat)abstract
- This paper presents a noise cancelling 0.7– 3.8GHz receiver front-end implemented in 65nm technology. The circuit has a main path consisting of a high input impedance gm-stage, current-mode passive mixers and baseband amplifiers, where the input match is provided by frequency translational negative feedback from baseband to RF input. An auxiliary path with tunable gain is introduced to cancel noise from the main path while maintaining linearity. The receiver front-end achieves a noise figure of 1.6–3.7dB and an IIP2 and IIP3 of >75dBm and >1dBm, respectively. The current consumption of the circuit is 22.8–34.9mA, from a 1.2V supply.
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| 41. |
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| 42. |
- Nejdel, Anders, et al.
(författare)
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A Positive Feedback Passive Mixer-First Receiver Front-End
- 2015
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Ingår i: 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). ; , s. 79-82
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a technique to reduce the noise figure of a passive mixer-first receiver front-end. By using lower than 50Ω switch resistance in the current-mode passive mixer and introducing a positive feedback from baseband to the RF-input, it can be well matched close to fLO while achieving a noise figure below 3dB, which is otherwise a fundamental limit. A quadrature front-end prototype for a direct conversion receiver has been implemented in 65nm CMOS, occupying an active area of 0.23mm2 with a frequency operation ranging from 0.7 to 3.8GHz. The prototype achieves a minimum noise figure of 2.5dB, an out-of-band 1dB compression point of +3dBm, with IIP3 and IIP2 exceeding +26 and +65dBm, respectively. The current consumption from a 1.2V supply is between 22.8 and 62.8mA, depending on frequency operation.
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| 43. |
- Nilsson, Peter, et al.
(författare)
-
Lessons from Ten Years of the International Master’s Program in System-on-Chip
- 2014
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Konferensbidrag (refereegranskat)abstract
- In July 2000 the five-year Swedish national “Socware Research & Education Program” was started. One of the aims of the program was to develop an innovative unique educational curriculum in System-on-Chip design. The program was targeted at undergraduate and graduate. In total the program received USD $15 million funding. In 2005 the program entered a new phase; more than 500 Master’s students were admitted and 30 PhD students were funded. Cooperation between the System-on-Chip Master’s programs in Lund, Linköping, and Stockholm was already well- established and the program continued in all three locations as an international Master of Science program in System-on-Chip, with local funding from the participating universities. Between 2003 and 2013 there were 3500 applicants to the program in Lund, an average of 350 applicants per year, of these 250 (8%) were accepted. This paper focuses on the international Master of Science Program in System-on-Chip at Lund University, Sweden.
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| 44. |
- Pourakbar, Mohammadreza, et al.
(författare)
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An LC-Based Tunable Low-Isolation Device for Adaptive Duplexers
- 2013
-
Ingår i: [Host publication title missing]. ; , s. 1-4
-
Konferensbidrag (refereegranskat)abstract
- An LTE-enabled smartphone is a software-defined radio system that must cover a large number of frequency bands with different duplex differences. A proposed adaptive wideband duplexer needs a circulator to create the required initial isolation. To replace this an LC-based tunable low-isolation device is presented in this paper, providing the required tuning range for LTE Band I, II, III and VII. The circuit is implemented in a 130nm Silicon-on-Insulator (SOI) process and provides an isolation exceeding 30dB at both transmit and receive frequencies of each specified LTE frequency band. The insertion loss from PA output to antenna port is below 2dB in LTE band I. The fabricated circuit occupies an area of 2.0mm×1.2mm.
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| 45. |
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| 46. |
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| 47. |
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| 48. |
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| 49. |
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| 50. |
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