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  • Karimi, E., et al. (author)
  • Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model
  • 2015
  • In: Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479986699 ; , s. 283-288
  • Conference paper (peer-reviewed)abstract
    • A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement.
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  • Result 1-1 of 1
Type of publication
conference paper (1)
Type of content
peer-reviewed (1)
Author/Editor
Rahmani, Amir (1)
Liljeberg, P. (1)
Karimi, E. (1)
Haghbayan, M. -H (1)
Navabi, Z. (1)
Tabandeh, M. (1)
University
Royal Institute of Technology (1)
Language
English (1)
Research subject (UKÄ/SCB)
Engineering and Technology (1)
Year
2015 (1)

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