| 1. |
- Björk, Magnus, 1977, et al.
(författare)
-
Exposed Datapath for Efficient Computing
- 2006
-
Rapport (övrigt vetenskapligt/konstnärligt)abstract
- We introduce FlexCore, which is the first exemplar of a processor based on the FlexSoC processor paradigm. TheFlexCore utilizes an exposed datapath for increased performance. Microbenchmarks yield a performance boost of a factor of two over a traditional five-stage pipeline with the same functional units as the FlexCore.We describe our approach to compiling for the FlexCore.A flexible interconnect allows the FlexCore datapath to bedynamically reconfigured as a consequence of code generation. Additionally, specialized functional units may be introduced and utilized within the same architecture and compilation framework. The exposed datapath requires a wide control word. The conducted evaluation of two micro benchmarks confirms that this increases the instruction bandwidth and memory footprint. This calls for an efficient instruction decoding as proposed in the FlexSoC paradigm.
|
|
| 2. |
|
|
| 3. |
|
|
| 4. |
- Thuresson, Martin, 1977, et al.
(författare)
-
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
- 2009
-
Ingår i: Journal of Signal Processing Systems. - : Springer Science and Business Media LLC. - 1939-8018 .- 1939-8115. ; 57:1, s. 5-19
-
Tidskriftsartikel (refereegranskat)abstract
- We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Comprising the same datapath units found in a conventional five-stage pipeline, the FlexCore has an exposed datapath control and a flexible interconnect to allow the datapath to be dynamically reconfigured as a consequence of code generation. Additionally, the FlexCore allows specialized datapath units to be inserted and utilized within the same architecture and compilation framework.This study shows that, in comparison to a conventional five-stage general-purpose processor, the FlexCore is up to 40\% more efficient in terms of cycle count on a set of benchmarks from the embedded application domain. We show that both the fine-grained control and the flexible interconnect contribute to the speedup. Furthermore, our synthesized, placed and routed FlexCore offers savings both in energy and execution time.The exposed FlexCore datapath requires a wide control word. The conducted evaluation confirms that this increases the instruction bandwidth and memory footprint. This calls for efficient instruction decoding as proposed in the FlexSoC framework.
|
|
| 5. |
- Thuresson, Martin, 1977, et al.
(författare)
-
A Flexible Code-Compression Scheme using Partitioned Look-Up Tables
- 2009
-
Ingår i: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). - Berlin, Heidelberg : Springer Berlin Heidelberg. - 1611-3349 .- 0302-9743. - 3540929894 ; 5409 LNCS, s. 95-109
-
Konferensbidrag (refereegranskat)abstract
- Wide instruction formats make it possible to control microarchitecture resources more precisely by the compiler by either enabling more parallelism (VLIW) or by saving power. Unfortunately, wide instructions impose a high pressure on the memory system due to an increased instruction-fetch bandwidth and a larger code working set/footprint. This paper presents a code compression scheme that allows the compiler to select what subset of a wide instruction set to use in each program phase at the granularity of basic blocks based on a profiling methodology. The decompression engine comprises a set of tables that convert a narrow instruction into a wide instruction in a dynamic fashion. The paper also presents a method for how to configure and dimension the decompression engine and how to generate a compressed program with embedded instructions that dynamically manage the tables in the decompression engine. We find that the 77 control bits in the original FlexCore instruction format can be reduced to 32 bits offering a compression of 58% and a modest performance overhead of less than 1% for management of the decompression tables.
|
|
| 6. |
- Thuresson, Martin, 1977, et al.
(författare)
-
A Flexible Code Compression Scheme using Partitioned Look-Up Tables
- 2008
-
Rapport (övrigt vetenskapligt/konstnärligt)abstract
- Wide instruction formats make it possible to controlmicroarchitecture resources more finely by enabling more parallelism(VLIW) or by utilizing the microarchitecture more efficiently byexposing the control to the compiler. Unfortunately, wideinstructions impose a higher pressure on the memory system due to anincreased instruction-fetch bandwidth and a larger code workingset/footprint.This paper presents a code compression scheme that allows thecompiler to select what subset of the wide instruction set to usein each program phase at the granularity of basic blocks based on aprofiling methodology. The decompression engine comprises a set oftables that convert a narrow instruction into a wide instruction ina dynamic fashion. The paper also presents a method for how toconfigure and dimension the decompression engine and how togenerate a compressed program with embedded instructions thatdynamically manage the tables in the decompression engine.We find that the 77 control bits in the original FlexCoreinstruction format can be reduced to 32 bits offering a compressionof 58% and a modest performance overhead of less than 1% formanagement of the decompression tables.
|
|
| 7. |
|
|
| 8. |
- Thuresson, Martin, 1977
(författare)
-
Compression Techniques for Code Size and Data Bandwidth Reduction
- 2006
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- A challenge in the design of high performance computer systems is how to transferdata efficiently between main memory and the faster and smaller memory located onthe processor chip. Main memory holds both the program to be executed and the datait needs to perform its tasks.This thesis focuses on how compression techniques can be used to store programsmore efficiently and how the data can be encoded in such a way that the effective bandwidthof the link between memory and the processor chip is improved. In the first part of the thesis, different dictionary based compression schemes areevaluated and a new flexible scheme for efficient compression and execution of compressedprograms is proposed. Since some sequences of instructions are more commonthan others, it is possible to reduce the memory needed for the program with little hardwareoverhead. In order to transfer data efficiently, this thesis also analyzes and classifies what typesof value locality we can exploit in the data. Current state-of-the-art compression techniquesare analyzed in the context of this categorization. Using this information, I showthat it is possible to efficiently combine different techniques that work on different typesof locality into a more efficient compression algorithm.Finally, I identify that the data-link compression schemes scale poorly with the numberof nodes in a multiprocessor system. By studying frequent value encoding in such aframework I show that in some configurations, it is possible to reuse frequent values ateach node and achieve significantly better bandwidth reductions than the baseline case.
|
|
| 9. |
- Thuresson, Martin, 1977
(författare)
-
Compression Techniques for Improved Bandwidth and Static Code Size in Computer Systems
- 2008
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Technological improvements in integrated circuits have for a longtime allowed the performance of computer chips to growexponentially, allowing for more and more advancedsystems. Unfortunately, the I/O-pins connecting the processorcore/cores with memory and other devices have not seen the samerate of improvement. In this thesis I study the opportunities andchallenges with using compression to help solve some of thechallenges that have emerged. These include reducing thebandwidth needed and the static code size.The first part of the thesis addresses data-link compression. Bystudying the data transferred between the last-level cache andmain memory, several types of localities that can be used tocompress the data are identified. Current state-of-the-artcompression techniques are analyzed in the context of thiscategorization. Using this categorization, I show that it ispossible to combine techniques that work on different types oflocality into a more efficient compression algorithm. Moreover, Ishow how stateful compression schemes can be implemented inmulti-node systems.This thesis also considers efficient program representation. Inmost programs, identical sequences of instructions often appearin several places, making dictionary based compression anefficient scheme for reducing the static code size. In thisthesis I propose a new, more flexible scheme in which similarsequences of instructions can be represented by the samedictionary entry and executed with low hardware overhead.Finally, a code compression scheme targeting wide instructionformats is presented. The scheme is based on dynamic look-uptables, which allow the compiler to adapt the compression todifferent phases of the application. Also presented is amethodology for dimensioning the decompression engine and analgorithm for generating compressed programs that dynamicallymanage the look-up tables with little run-time performanceoverhead. The compression scheme is evaluated using FlexCore, anarchitecture with exposed datapath control, and shown toefficiently reduce the control-bits of the instruction word bymore than 50%.
|
|
| 10. |
|
|
| 11. |
|
|
| 12. |
|
|
| 13. |
|
|
| 14. |
|
|
