| 1. |
- Salami, B., et al.
(författare)
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LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing
- 2020
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Ingår i: PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020). - 1530-1591. - 9783981926347 ; , s. 169-174
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Konferensbidrag (refereegranskat)abstract
- The LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC, balanced with the security and resilience challenges. LEGaTO is an ongoing three-year EU H2020 project started in December 2017.
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| 2. |
- Armejach, A., et al.
(författare)
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Techniques to Improve Performance in Requester-Wins Hardware Transactional Memory
- 2013
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Ingår i: Transactions on Architecture and Code Optimization. - 1544-3973 .- 1544-3566. ; 10:4, s. articlenr, 42-
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Tidskriftsartikel (refereegranskat)abstract
- The simplicity of requester-wins Hardware Transactional Memory (HTM) makes it easy to incorporate in existing chip multiprocessors. Hence, such systems are expected to be widely available in the near future. Unfortunately, these implementations are prone to suffer severe performance degradation due to transient and persistent livelock conditions. This article shows that existing techniques are unable to mitigate this degradation effectively. It then proposes and evaluates four novel techniques-two software-based that employ information provided by the hardware and two that require simple core-local hardware additions-which have the potential to boost the performance of requester-wins HTM designs substantially.
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| 3. |
- Negi, Anurag, 1980, et al.
(författare)
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Transactional prefetching: Narrowing the window of contention in hardware transactional memory
- 2012
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Ingår i: Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. - New York, NY, USA : ACM. - 1089-795X. ; , s. 181-190
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Konferensbidrag (refereegranskat)abstract
- Memory access latency is the primary performance bottle-neck in modern computer systems. Prefetching data before it is needed by a processing core allows substantial performance gains by overlapping significant portions of memory latency with useful work. Prior work has investigated this technique and measured potential benefits in a variety of scenarios. However, its use in speeding up Hardware Transactional Memory (HTM) has remained hitherto unexplored. In several HTM designs transactions invalidate speculatively updated cache lines when they abort. Such cache lines tend to have high locality and are likely to be accessed again when the transaction re-executes. Coarse grained transactions that update several cache lines are particularly susceptible to performance degradation even under moderate contention. However, such transactions show strong locality of reference, especially when contention is high. Prefetching cache lines with high locality can, therefore, improve overall concurrency by speeding up transactions and, thereby, narrowing the window of time in which such transactions persist and can cause contention. Such transactions are important since they are likely to form a common TM use-case. We note that traditional prefetch techniques may not be able to track such lines adequately or issue prefetches quickly enough. This paper investigates the use of prefetching in HTMs, proposing a simple design to identify and request prefetch candidates, and measures performance gains to be had for several representative TM workloads.
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