| 1. |
- Duan, Ningyuan, et al.
(författare)
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Reduction of NiGe/n- and p-Ge Specific Contact Resistivity by Enhanced Dopant Segregation in the Presence of Carbon During Nickel Germanidation
- 2016
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Ingår i: IEEE Transactions on Electron Devices. - : IEEE. - 0018-9383 .- 1557-9646. ; 63:11, s. 4546-4549
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Tidskriftsartikel (refereegranskat)abstract
- This brief explores the specific contact resistivity (rho(c)) of NiGe/n- and p-Ge contacts with and without carbon pregermanidation implantation. It is found that in the presence of carbon, not only the thermal stability of NiGe films is improved, but also the rho(c) of the NiGe/n- and p-Ge contacts is reduced remarkably due to enhanced phosphorus (P) and boron (B) dopant segregation (DS) at the NiGe/Ge interface after nickel germanidation. At 500 degrees C germanidation temperature, the.c values are reduced from 1.1 x 10(-4) Omega-cm(2) and 2.9 x 10(-5) Omega-cm(2) for NiGe/n- and p-Ge contacts without carbon to 7.3 x 10(-5) Omega-cm(2) and 1.4 x 10(-5) Omega-cm(2) for their counterparts with carbon, respectively.
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| 2. |
- Li, Junjie, et al.
(författare)
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A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm
- 2020
-
Ingår i: Materials. - : MDPI AG. - 1996-1944. ; 13:3
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Tidskriftsartikel (refereegranskat)abstract
- Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.
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| 3. |
- Du, Yong, et al.
(författare)
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Investigation of the Heteroepitaxial Process Optimization of Ge Layers on Si (001) by RPCVD
- 2021
-
Ingår i: Nanomaterials. - : MDPI AG. - 2079-4991. ; 11:4
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Tidskriftsartikel (refereegranskat)abstract
- This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski-Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it's threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 degrees C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 x 10(7) cm(-2)). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.
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| 4. |
- Du, Yong, et al.
(författare)
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Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon
- 2022
-
Ingår i: Nanomaterials. - : MDPI AG. - 2079-4991. ; 12:5
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Forskningsöversikt (refereegranskat)abstract
- Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.
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| 5. |
- Wang, Guilei, et al.
(författare)
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Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)
- 2020
-
Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 26-33
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Tidskriftsartikel (refereegranskat)abstract
- In this study, the integration of Si 1−x Ge x (50% ≤ x ≤ 60%) selective epitaxy on source/drain regions in 10 nm node FinFET has been presented. One of the major process issues was the sensitivity of Si-fins’ shape to ex- and in-situ cleaning prior to epitaxy. For example, the sharpness of Si-fins could easily be damaged during the wafer washing. The results showed that a DHF dip before the normal cleaning, was essential to clean the Si-fins while in-situ annealing in range of 780–800 °C was needed to remove the native oxide for high epitaxial quality. Because of smallness of fins, the induced strain by SiGe could not be directly measured by X-ray beam in a typical XRD tool in the lab or even in a Synchrotron facility. Further analysis using nano-beam diffraction technique in high-resolution transmission electron microscope also failed to provide information about strain in the FinFET structure. Therefore, the induced strain by SiGe was simulated by technology computer-aided design program and the Ge content was measured by using energy dispersive spectroscopy. Simulation results showed 0.8, 1 and 1.3 GPa for Ge content of 40%, 50% and 60%, respectively. A kinetic gas model was also introduced to predict the SiGe profile on Si-fins with sharp triangular shape. The input parameters in the model includes growth temperature, partial pressure of the reactant gases and the exposed Si coverage in the chip area.
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| 6. |
- Wang, Guilei, et al.
(författare)
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Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology
- 2016
-
Ingår i: Microelectronic Engineering. - : Elsevier. - 0167-9317 .- 1873-5568. ; 163, s. 49-54
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Tidskriftsartikel (refereegranskat)abstract
- In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14 nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si1-xGex (0.35 <= x <= 0.40) with boron concentration of 1 x 10(20) cm(-3) was used to elevate the source/drain of the transistors. The epi-quality, layer profile and strain amount of the selectively grown SiGe layers were also investigated by means of various characterizations. A series of prebaking experiments were performed for temperatures ranging from 740 to 825 degrees C in order to in situ clean the Si fins prior to the epitaxy. The results showed that the thermal budget needs to be limited to 780-800 degrees C in order to avoid any damages to the shape of Si fins but to remove the native oxide effectively which is essential for high epitaxial quality. The Ge content in SiGe layers on Si fins was determined from the strain measured directly by reciprocal space mappings using synchrotron radiation. Atomic layer deposition technique was applied to fill the gate trench with W using WF6 and B2H6 precursors. By such an AID approach, decent growth rate, low resistivity and excellent gap filling capability of W in pretty high aspect-ratio gate trench was realized. The as-fabricated FinFETs demonstrated decent electrical characteristics.
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| 7. |
- Xiong, Wenjuan, et al.
(författare)
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SiNx films and membranes for photonic and MEMS applications
- 2020
-
Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 90-97
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Tidskriftsartikel (refereegranskat)abstract
- This work presents a novel process to form SiN x films and process for membranes with excellent mechanical properties for micro-electro-mechanical systems application as well as integration as IR waveguide for photonic application. The SiN x films were fabricated in SiNgen apparatus which is a single wafer chamber equipment compared to conventional low pressure chemical vapor deposition furnace process. The films showed low stress, good mechanical properties, but the synthesis also eradicates the issues of particle contamination. Through optimizing of the growth parameters and post annealing profile, low stress (40 Mpa) SiN x film could be finally deposited when annealing temperature rose up to 1150 °C. The stress relaxation is a result of more Si nano-crystalline which was formed during annealing, according to the FTIR results. The mechanical properties, Young’s modulus and hardness, were 210 Gpa and 20 Gpa respectively. For the waveguide application, a stack of three layers, SiO 2 /SiN x /SiO 2 was formed where the optimized layer thicknesses were used for minimum optical loss according to simulation feedback. After deposition of the first two layers in the stack, the samples were annealed in range of 900–1150 °C in order to release the stress. Chemical mechanical polish technique was applied to planarize the nitride layer prior to the oxide cladding layer. Such wafers can be used to bond to Si or Ge to manufacture advanced substrates.
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| 8. |
- Zhao, Xuewei, et al.
(författare)
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Design impact on the performance of Ge PIN photodetectors
- 2020
-
Ingår i: Journal of materials science. Materials in electronics. - : Springer. - 0957-4522 .- 1573-482X. ; 31:1, s. 18-25
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Tidskriftsartikel (refereegranskat)abstract
- This article presents the impact of epitaxial quality, contact resistance and profile of Ge PIN photodetectors (PDs) on dark current and responsivity. The PD structures were processed with either selectively grown Ge with integrated waveguides on SOI wafer or globally grown Ge on the entire wafer. The contact resistance was lowered by introducing NiGe layer prior to the metallization. The n-type doped Ge PIN structure was formed by ion implantation and the contact resistivity was estimated to 2.6x10(-4) ohm cm(2). This value is rather high and it is believed to be due to fomation of defects during implantation. The results show a minor difference in dark currents for selectively and globally grown PDs but in both types, it depends on detector area and the epitaxial quality of Ge. For example, the threading dislocation density (TDD) in non-selectively grown PDs with thickness of 1 mu m was estimated to be 10(6) cm(-2) yielding relatively low dark currents while it dramatically changes for PDs with thinner Ge layers where TDD increases to 10(8) cm(-2) and the dark current levels increase almost by 1.5 magnitude. Surprisingly, for selectively grown PDs with Ge thickness of 500 nm, TDD was still low resulting in low dark currents. The dark current densities at -1 V bias of non-selectively and selectively grown PDs with optimized profile were measured to be 5 mA/cm(2) and 47 mA/cm(2), respectively, while the responsivity of these detectors were 0.17 A/W and 0.46 A/W at lambda similar to 1.55 mu m, respectively. Excellent performance for selectively grown PD shows an appropriate choice for detection of 1.55 mu m wavelength.
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| 9. |
- Li, You, et al.
(författare)
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Si and SiGe Nanowire for Micro-Thermoelectric Generator : A Review of the Current State of the Art
- 2021
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Ingår i: Frontiers in Materials. - : Frontiers Media SA. - 2296-8016. ; 8
-
Tidskriftsartikel (refereegranskat)abstract
- In our environment, the large availability of wasted heat has motivated the search for methods to harvest heat. As a reliable way to supply energy, SiGe has been used for thermoelectric generators (TEGs) in space missions for decades. Recently, micro-thermoelectric generators (μTEG) have been shown to be a promising way to supply energy for the Internet of Things (IoT) by using daily waste heat. Combining the predominant CMOS compatibility with high electric conductivity and low thermal conductivity performance, Si nanowire and SiGe nanowire have been a candidate for μTEG. This review gives a comprehensive introduction of the Si, SiGe nanowires, and their possibility for μTEG. The basic thermoelectric principles, materials, structures, fabrication, measurements, and applications are discussed in depth.
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| 10. |
- Liu, Jinbiao, et al.
(författare)
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Study of n-type doping in germanium by temperature based PF+ implantation
- 2020
-
Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 161-166
-
Tidskriftsartikel (refereegranskat)abstract
- Incorporation of P in germanium was studied by using PF+ molecular implantation in a range from room temperature to 400 °C. The presence of F acted as a barrier for P in-diffusion and resulted in higher activation of P at room temperature. In addition, it is found that when the implantation is performed at 400 °C, the residual defects are stable and the diffusion of P can be blocked during activation annealing. Therefore, the final junction depth could be well controlled by the implantation process itself. This method is meaningful for the shallow junction formation in sub 14-nm Ge-based FinFETs or high-performance photodetectors.
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| 11. |
- Liu, Qingbo, et al.
(författare)
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Effects of carbon pre-germanidation implant into Ge on the thermal stability of NiGe films
- 2015
-
Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 133, s. 6-10
-
Tidskriftsartikel (refereegranskat)abstract
- In this work, the effects of carbon pre-germanidation implant into Ge on the properties of NiGe films were systematically investigated. NiGe films with carbon pre-germanidation implant to doses varying from 0 to 6 x 10(15) cm(-2) were characterized by means of sheet resistance measurement, X-ray diffraction (XRD), scanning electron microscopy (SEM), cross-sectional transmission electron microscope (X-TEM) and secondary ion mass spectroscopy (SIMS). The presence of C atoms is proved to significantly enhance the thermal stability of NiGe by about 100 degrees C as well as to change the preferred orientations of polycrystalline NiGe. The homogenous redistribution of C atoms within NiGe films and the segregation of C atoms at the NiGe/Ge interface is responsible for the improved thermal stability of NiGe films.
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| 12. |
- Liu, Qingbo, et al.
(författare)
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Effects of Carbon Pre-Germanidation Implantation on the Thermal Stability of NiGe and Dopant Segregation on Both n- and p-Type Ge Substrate
- 2015
-
Ingår i: ECS Journal of Solid State Science and Technology. - : The Electrochemical Society. - 2162-8769 .- 2162-8777. ; 4:5, s. P119-P123
-
Tidskriftsartikel (refereegranskat)abstract
- In this work, the effects of carbon pre-geramanidation implantation on the thermal stability of NiGe and dopant segregation on both ntype and p-type Ge substrate were investigated systematically. As-prepared NiGe films with carbon pre-germanidation implantation to different doses were characterized by means of sheet resistance measurement, X-ray diffraction (XRD), scanning electron microscopy (SEM), cross-sectional transmission electron microscope (X-TEM) and secondary ion mass spectroscopy (SIMS). The presence of carbon is proved to improve the thermal stability of NiGe formed on both n-and p-type Ge significantly, as well as to lead to dopant segregation (DS) of P and B at the NiGe/Ge interface. The homogeneous distribution of C within NiGe films and stuffing of C atoms at the NiGe/Ge interface is responsible for the enhanced thermal stability of NiGe and DS of P and B during germanidation process. (C) The Author(s) 2015. Published by ECS. All rights reserved.
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| 13. |
- Qin, Changliang, et al.
(författare)
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Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 14 nm node FinFETs
- 2016
-
Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 124, s. 10-15
-
Tidskriftsartikel (refereegranskat)abstract
- A complete mapping of 14 nm FinFETs performance over 200 mm wafers was performed and the pattern dependency of SiGe selective growth was calculated using an empirical kinetic molecule model for the reactant precursors. The transistor structures were analyzed by conventional characterization tools and their performance was simulated by considering the process related variations. The applied model presents for the first time a powerful tool for transistor community to predict the SiGe profile and strain modulating over a processed wafer, independent of wafer size.
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| 14. |
- Qin, Changliang, et al.
(författare)
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Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs
- 2016
-
Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 123, s. 38-43
-
Tidskriftsartikel (refereegranskat)abstract
- In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF2 in SiGe layers. The overlap space between doping junction and channel region has great effect on the device's performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer ID-VG curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on-off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.
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| 15. |
- Radamson, Henry H., et al.
(författare)
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Miniaturization of CMOS
- 2019
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Ingår i: Micromachines. - : MDPI AG. - 2072-666X. ; 10:5
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Tidskriftsartikel (refereegranskat)abstract
- When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
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| 16. |
- Radamson, Henry H., et al.
(författare)
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State of the Art and Future Perspectives in Advanced CMOS Technology
- 2020
-
Ingår i: Nanomaterials. - : MDPI AG. - 2079-4991. ; 10:8
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Forskningsöversikt (refereegranskat)abstract
- The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
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| 17. |
- Radamson, Henry H., et al.
(författare)
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The Challenges of Advanced CMOS Process from 2D to 3D
- 2017
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Ingår i: Applied Sciences. - : MDPI AG. - 2076-3417. ; 7:10
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Forskningsöversikt (refereegranskat)abstract
- The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.
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| 18. |
- Wang, Guilei, et al.
(författare)
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Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors
- 2017
-
Ingår i: Nanoscale Research Letters. - : Springer. - 1931-7573 .- 1556-276X. ; 12
-
Tidskriftsartikel (refereegranskat)abstract
- In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective Si1-xGex growth (0.35 <= x <= 0.40) with boron concentration of 1-3 x 10(20) cm(-3) was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance.
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| 19. |
- Wang, Guilei, et al.
(författare)
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Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology
- 2015
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 103, s. 222-228
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Tidskriftsartikel (refereegranskat)abstract
- SiGe has been widely used as stressors in source/drain (S/D) regions of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) to enhance the channel mobility. In this study, selectively grown Si1-xGex (0.33 <= x <= 0.35) with boron concentration of 1 x 10(20) cm(-3) was used to elevate the S/D regions on bulk FinFETs in 14 nm technology node. The epitaxial quality of SiGe layers, SiGe profile and the strain amount of the SiGe layers were investigated. In order to in-situ clean the Si-fins before SiGe epitaxy, a series of prebaking experiments at temperature ranging from 740 to 825 degrees C were performed. The results showed that the thermal budget needs to be limited to 780-800 degrees C in order to avoid any damage to the shape of Si-fins but to remove the native oxide which is essential for high epitaxial quality. In this study, a kinetic gas niodel was also applied to predict the SiGe growth profile on Si-fins with trapezoidal shape. The input parameters for the model include growth temperature, partial pressures of reactant gases and the chip layout. By knowing the epitaxial profile, the strain to the Si-fins exerted by SiGe layers can be calculated. This is important in understanding the carrier transport in the FinFETs. The other benefit of the modeling is that it provides a cost-effective alternative for epitaxy process development as the SiGe profile can be readily predicted for any chip layout in advance.
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| 20. |
- Wang, Guilei, et al.
(författare)
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pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology
- 2017
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Ingår i: Nanoscale Research Letters. - : SPRINGER. - 1931-7573 .- 1556-276X. ; 12
-
Tidskriftsartikel (refereegranskat)abstract
- In this paper, pMOSFETs featuring atomic layer deposition (ALD) tungsten (W) using SiH4 and B2H6 precursors in 22 nm node CMOS technology were investigated. It is found that, in terms of threshold voltage, driving capability, carrier mobility, and the control of short-channel effects, the performance of devices featuring ALD W using SiH4 is superior to that of devices featuring ALD W using B2H6. This disparity in device performance results from different metal gate-induced strain from ALD W using SiH4 and B2H6 precursors, i.e. tensile stresses for SiH4 (similar to 2.4 GPa) and for B2H6 (similar to 0.9 GPa).
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