| 1. |
- Wilk, Julie, 1962-, et al.
(författare)
-
Citizen Sensing Stakeholder Interaction Manual
- 2021
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Rapport (populärvet., debatt m.m.)abstract
- This stakeholder interaction manual was prepared in the ERA4CS project: Citizen Sensing - Urban climate resilience through a Participatory Risk Management System(PRMS). The Participatory Risk Management System includes an app by which end-users upload reports (weather observations, eventual impacts, level of personal comfort accompanied by comments and/or images) and a spatial-temporal visualization platform (the CitizenSensing web-portal) that allows users to view, explore and analyze the reports (see Navarra et al. 2020). The aim of the manual is to guide stakeholder interactions within the project to assess and gain deeper insight into the perceptions, priorities and reflections of stakeholders2 that were involved in the co-design process and organize the end-user3 campaigns.The “Getting Started” section contains general information about participants, workshops, aims, outcomes, preparations, equipment, opening and closing workshops and communication. The following sections contain participatory exercises that could be performed with stakeholders and/or end-users to inform and guide the co-design process of CitizenSensing researchers and municipal through the set-up, testing and assessment of the PRMS. The exercises are organized under a number of workshops4. These would be performed with several participants, but the same exercises could be performed at or smaller meetings with a few people or individuals.The workshop sections contain a number of interactive exercises that cover a number of themes: Climate-related issues and project pre-conditions (Workshop 1A)Risks, sensitive groups and locations and climate-related variables (Workshop 1B)Sensor networks, databases and municipal tasks (Workshop 2A)App requirements, critical levels and recommendations (Workshop 2B)Assessing possibilities for measurement/observation campaigns (Workshop 3)Designing the end-user campaigns (Workshop 4)Preparing the end-user campaigns (Workshop 5)Initiating the end-user campaigns (Workshop 6)Concluding the end-user campaigns (Workshop 7).Assessing stakeholder perspectives: Workshop (Workshop 8)Assessing stakeholder perspectives: InterviewsAppendices I and II contain pre-campaign and post-campaign surveys to be conducted at Workshops 4 and 5. Appendix III contains an interview guide that could be used in Workshops 8 or 9. Appendix IV contains a guide to exploring the web-portal that could be used in Workshops 8 or 9.
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| 2. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS
- 2010
-
Ingår i: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 29-32
-
Konferensbidrag (refereegranskat)abstract
- In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inherent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inherent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit devices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.
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| 3. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
-
A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
- 2010
-
Ingår i: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10. - Tampere : www.ieee.org. - 9781424489718 - 9781424489725 ; , s. 1-4
-
Konferensbidrag (refereegranskat)abstract
- This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.
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| 4. |
- Afzal, Nadeem, et al.
(författare)
-
A Low-Complexity LMMSE Based Channel Estimation Algorithm for Multiple Standards in Mobile Terminals
- 2010
-
Ingår i: Proceedings of the Swedish System On Chip Conference, SSOCC 2010.
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- A less complex and generic channel estimation algorithm for long term evolution (LTE) and digital video broadcasting-handheld (DVB-H) downlink standards, is proposed. The technique, here referred to as minimum mean square error sliding window (MSW) technique, obtains less computational complexity than previous mean squared error (MSE) algorithms [3] at the cost of some 0.3 dB less SNR. The computational complexity is decreased by a factor 3 for the LTE 5-MHz downlink case and by 30 for the DVB-H standard case. Simulated results in terms of mean squared error and bit error rates are presented for a quadrature phase-shift keying (QPSK) systems with interleaving and coding of the data. All simulations are done at the behaviolar-level level.
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| 5. |
- Afzal, Nadeem, et al.
(författare)
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Study of modified noise-shaper architectures for oversampled sigma-delta DACs
- 2010
-
Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.
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| 6. |
- Alvbrant, Joakim, 1973-
(författare)
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A study on emerging electronics for systems accepting soft errors
- 2016
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Moore’s law has until today mostly relied on shrinkage of the size of the devices inintegrated circuits. However, soon the granularity of the atoms will set a limit together with increased error probability of the devices. How can Moore’s law continue in thefuture? To overcome the increased error rate, we need to introduce redundancy. Applyingmethods from biology may be a way forward, using some of the strategies that transformsan egg into a fetus, but with electronic cells.A redundant system is less sensitive to failing components. We define electronic clayas a massive redundancy system of interchangeable and unified subsystems. We show how a mean voter, which is simpler than a majority voter, impact a redundant systemand how optimization can be formalized to minimize the impact of failing subsystems.The performance at given yield can be estimated with a first order model, without the need for Monte-Carlo simulations. The methods are applied and verified on a redundant finite-impulse response filter.The elementary circuit behavior of the memristor, ”the missing circuit element”, is investigated for fundamental understanding and how it can be used in applications. Different available simulation models are presented and the linear drift model is simulated with Joglekar-Wolf and Biolek window functions. Driven by a sinusoidal current, the memristor is a frequency dependent component with a cut-off frequency. The memristor can be densely packed and used in structures that both stores and compute in the same circuit, as neurons do. Surrounding circuit has to affect (write) and react (read) to the memristor with the same two terminals.We looked at artificial neural network for pattern recognition, but also for self organization in electronic cell array. Finally we look at wireless sensor network and how such system can adopt to the environment. This is also a massive redundant clay-like system.Future electronic systems will be massively redundant and adaptive. Moore’s law will continue, not based on shrinking device sizes, but on cheaper, numerous, unified and interchangeable subsystems.
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| 7. |
- Alvbrant, Joakim, 1973-, et al.
(författare)
-
Study and Simulation Example of a Redundant FIR Filter
- 2012
-
Ingår i: Proceedings 30th Norchip Conference. - : IEEE. - 9781467322225 - 9781467322218 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture.
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| 8. |
- Andersson, Niklas, 1975-, et al.
(författare)
-
A strategy for implementing dynamic element matching in current-steering DACs
- 2000
-
Ingår i: Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on. - : IEEE. - 0780359755 ; , s. 51-56
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC)
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| 9. |
- Andersson, Niklas, 1975-, et al.
(författare)
-
Comparison of Different Dynamic Element Matching Techniques for Wideband CMOS DACs
- 1999
-
Ingår i: Proceedings of the 17th Norchip Conference.
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In the field of dynamic element matching, DEM, techniques, some ”new” important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.
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| 10. |
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| 11. |
- Andersson, Ola, 1976-, et al.
(författare)
-
Characterization of a CMOS current-steering DAC using state-space models
- 2000
-
Ingår i: Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on. - : IEEE. - 0780364759 ; , s. 668-671 vol.2
-
Konferensbidrag (refereegranskat)abstract
- Performance limitations on current-steering digital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, matching, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic nonidealities. Simulation results are presented and compared to measurement results. The model can be used for fast performance estimation of D/A converters
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| 12. |
- Andersson, Ola, 1976-, et al.
(författare)
-
Digital-to-analog converter having error correction
- 2002
-
Patent (populärvet., debatt m.m.)abstract
- The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n−1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.
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| 13. |
- Andersson, Ola, 1976-, et al.
(författare)
-
Modeling of the Influence of Graded Element Matching Errors in CMOS Current-Steering DACs
- 1999
-
Ingår i: Proceedings of the 17th Norchip Conference.
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In analog and mixed-mode circuits the matching between circuit elements is crucial.For example, in binary encoded digital-to-analog converters (DACs) the matchingbetween different bit weights can set the limit on the performance. Related to earlier workmodeling the influence of stochastic matching, the influence of graded element matching errorson the performance of current-steering DACs is shown. Presented are calculated results thatcorrelate very well with simulated results. As performance measures we use both static measuresas DNL and INL as well as frequency domain parameters as SNDR and SFDR. This discussioncan also be applied to other DAC structures, for example switched-capacitor.
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| 14. |
- Andersson, Ola, 1976-, et al.
(författare)
-
Spectral shaping of DAC nonlinearity errors through modulation of expected errors
- 2001
-
Ingår i: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on. - : IEEE. - 0780366859 ; , s. 417-420
-
Konferensbidrag (refereegranskat)abstract
- Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included
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| 15. |
- Domènech-Gil, Guillem, Mr. Doctor, et al.
(författare)
-
Electronic Nose for Improved Environmental Methane Monitoring
- 2024
-
Ingår i: Environmental Science and Technology. - : AMER CHEMICAL SOC. - 0013-936X .- 1520-5851. ; 58, s. 352-361
-
Tidskriftsartikel (refereegranskat)abstract
- Reducing emissions of the key greenhouse gas methane (CH4) is increasingly highlighted as being important to mitigate climate change. Effective emission reductions require cost-effective ways to measure CH4 to detect sources and verify that mitigation efforts work. We present here a novel approach to measure methane at atmospheric concentrations by means of a low-cost electronic nose strategy where the readings of a few sensors are combined, leading to errors down to 33 ppb and coefficients of determination, R-2, up to 0.91 for in situ measurements. Data from methane, temperature, humidity, and atmospheric pressure sensors were used in customized machine learning models to account for environmental cross-effects and quantify methane in the ppm-ppb range both in indoor and outdoor conditions. The electronic nose strategy was confirmed to be versatile with improved accuracy when more reference data were supplied to the quantification model. Our results pave the way toward the use of networks of low-cost sensor systems for the monitoring of greenhouse gases.
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| 16. |
- Gao, YC, et al.
(författare)
-
Design and analysis of an oversampling D/A converter in DMT-ADSL systems
- 2002
-
Ingår i: Analog Integrated Circuits and Signal Processing. - Hingham, MA, USA : Kluwer Academic Publishers. - 0925-1030 .- 1573-1979. ; 32:3, s. 201-210
-
Tidskriftsartikel (refereegranskat)abstract
- Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 mum 3.3 V CMOS process and integrated into the whole DAC chip.
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| 17. |
- Gustavsson, Mikael, et al.
(författare)
-
CMOS Data Converters for Communications
- 2000
-
Bok (övrigt vetenskapligt/konstnärligt)abstract
- CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications.The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed.The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book.CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.
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| 18. |
- Holmbring, Staffan, et al.
(författare)
-
Elektronism : en flerårig resa genom tolv månader
- 2021
-
Bok (populärvet., debatt m.m.)abstract
- Temat i boken Elektronism ligger i tiden. Staffan Holmbring och J Jacob Wikner gör en tidsresa genom året. Funderingar kopplas ihop med månadernas karaktär. Naturvetenskapliga och filosofiska tankar uppstår och läsaren får följa dem under tidsresans gång. Elektronism tar vid där vår frågvishet slutar. Holmbring och Wikner ställer frågor på ett enkelt vis. Varför är vatten blött? Varför blir det aldrig blötare av att vattna på vatten?Elektronism är en fristående fortsättning där den förra boken Elektrosofi slutade. Resan har nu fortsatt från geografiska stopp till stopp i vår kalender. Staffan Holmbring är teknisk doktor i tillämpad fysik från Linköpings universitet. Kompetensen han fick därifrån har han bland annat använt i de företag som han har drivit från 80-talet med verksamheter inom tillämpad fysik och integrerad elektronik. Mycket intresserar honom utanför det naturvetenskapliga skrået, främst litteratur, filosofi och bildkonst. J Jacob Wikner är uppväxt i Borgholm, Öland. Dagarna fylls ofta med föreläsningar, kretskonstruktion och forskningsprojekt som spänner från den afrikanska landsbygden via kroppens elektriska signaler till röntgendetektorer. Intressena för en teknisk doktor, docent och biträdande professor kan vara många.
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| 19. |
- Holmbring, Staffan, et al.
(författare)
-
Elektrosofi : med avtryck från Öland
- 2019
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Bok (övrigt vetenskapligt/konstnärligt)abstract
- "nedslag från en tankeväckande resa på Öland. Vilka funderingar kan kopplas ihop med de platser som författarna besöker under resans gång? Vi får följa de naturvetenskapliga såväl som filosofiska tankar som uppstår längs resans väg."
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| 20. |
- Jalili, Armin, et al.
(författare)
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A nonlinearity error calibration technique for pipelined ADCs
- 2011
-
Ingår i: Integration. - Amsterdam, The Netherlands : Elsevier. - 0167-9260 .- 1872-7522. ; 44:3, s. 229-241
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.
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| 21. |
- Jalili, Armin, et al.
(författare)
-
Calibration of high-resolution flash ADCS based on histogram test methods
- 2010
-
Ingår i: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. - : IEEE. - 9781424481552 ; , s. 114-117
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.
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| 22. |
- Jalili, Armin, et al.
(författare)
-
Calibration of sigma-delta analog-to-digital converters based on histogram test methods
- 2010
-
Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
-
Konferensbidrag (refereegranskat)abstract
- In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.
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| 23. |
- Jalili, Armin, et al.
(författare)
-
Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs
- 2011
-
Ingår i: Microelectronics Journal. - Oxford, UK : Elsevier. - 0959-8324 .- 0026-2692. ; 42:1, s. 158-164
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a digital background calibration technique to compensate inter-channel gain and offset errors in parallel, pipelined analog-to-digital converters (ADCs). By using an extra analog path, calibration of each ADC channel is done without imposing any changes on the digitizing structure, i.e., keeping each channel completely intact. The extra analog path is simplified using averaging and chopping concepts, and it is realized in a standard 0.18‐μm CMOS technology. The complexity of the analog part of the proposed calibration system is same for a different number of channels.Simulation results of a behavioral 12-bit, dual channel, pipelined ADC show that offset and gain error tones are improved from −56.5 and −58.3 dB before calibration to about −86.7 and −103 dB after calibration, respectively.
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| 24. |
- Kifle, Yonatan Habteslassie, 1984-
(författare)
-
Studies On Design of Near-Field Wireless-Powered Biphase Implantable Stimulators
- 2022
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Portable and implantable electronics are becoming increasingly important in the healthcare sector. One of the challenges is to guarantee stable systems for longer periods of time. If we consider applications such as electrical nerve stimulation or implanted ion pumps, the requirements for, e.g., levels, duration, etc., vary over time, and there may be a need to be able to remotely reconfigure devices, which in turn extends the life of the implant. This dissertation studies the efficient healthcare wireless network, wireless power supply, and its use in implantable biomedical systems. The body-area network (BAN) and near-field communication (NFC) are studied. Several Application Specific Integrated Circuits (ASICs) solutions are implemented, manufactured, and characterized. ASICs for portable and implantable sensors and actuators still have high research value. In addition, advances in flexible, implantable inductive coils, along with near-field energy harvesting technology, have driven the development of wireless, implantable devices. The ASICs are used to initiate and generate controlled signals that govern actuators in multiple locations in the body. Electronics specifications may include operations related to tissue-specific absorption rate, stimulation duration or levels to avoid tissue temperature rise, power transmission distance, and controlled current or voltage drivers. In this work, the feasibility of BAN as a healthcare network has been investigated. The functionality of an existing BodyCom communication system was expanded, sensors and actuators are added. The system enables data transfer between several sensor nodes placed on a human body. In BAN, the information is propagated along the skin in a capacitive, electric field. The network was demonstrated with a sensor node (stretchable glove) and implantable ion pump (actuator) for drug delivery. With the stretchable glove, movement patterns could be captured, and ions were delivered from a reservoir in the ion pump. Furthermore, NFC is studied, and the advantages of NFC compared to BAN are discussed. An ST Microelectronics system was used together with a planar coil developed on a flexible plastic substrate to demonstrate the concept. The efficiency between the primary and secondary coils is measured and characterized. A temperature sensor was chosen as the implantable sensor, and the signal strength at several distances between the primary and secondary inductive coils is characterized. The next phase of the work focuses on the implementation of ASICs. The first proposed system describes a wirelessly powered peripheral nerve stimulator. The system contains a full-wave rectifier-based energy harvester that operates at 13.56 MHz with the option to select a stimulation current. The stimulation current can be selected in the range of 15 nA up to 1 mA. A reference clock is extracted from the AC input and used to synchronize the data and generate the required control. In addition, a state machine is used to generate the time parameters required for cathodic and anodic nerve stimulation. The design is fabricated in the standard 180 nm CMOS process and is 0.22 mm2 large, excluding an integrated 3.6 nF capacitor. The chip is measured to verify the energy harvester, power cells, and timing control logic with an input amplitude |VAC | = 3 V and a load of 1 kΩ. Subsequently, a multichannel system was developed that makes it possible to dynamically set the biphase simulation profile. The amplitude modulated data packets transmitted through the inductively coupled interface are demodulated, and the information is extracted. The data stream is then used to generate control signals that activate the desired configuration (channel, stream, time, etc.).
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| 25. |
- Morales Chacón, Oscar, 1985-, et al.
(författare)
-
A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS
- 2020
-
Ingår i: 2020 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). - : IEEE. - 9781728192260
-
Konferensbidrag (refereegranskat)abstract
- Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-mn CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220 mW for 58.6-pJ energy consumption per sample.
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| 26. |
- Morales Chacon, Oscar Andres, 1985-, et al.
(författare)
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Analysis of energy consumption bounds in CMOS current-steering digital-to-analog cosnverters
- 2022
-
Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer. - 0925-1030 .- 1573-1979. ; 111, s. 339-351
-
Tidskriftsartikel (refereegranskat)abstract
- In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 2(2ENOB), whereas the speed-bound increases by 2(ENOB-2) and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2(ENOB-1). The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, f(s)/2.
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| 27. |
- Morales Chacón, Oscar, et al.
(författare)
-
A digital switching scheme to reduce DAC glitches using code-dependent randomization
- 2021
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Ingår i: 2021 IEEE Nordic Circuits and Systems Conference (NorCAS). - : IEEE. - 9781665407120 ; , s. 1-5
-
Konferensbidrag (refereegranskat)abstract
- A digital switching scheme to reduce glitches and induce code-dependent randomization in digital-to-analog converters (DACs) is presented. The switching scheme is capable of generating a thermometer-like decoded bit sequence from a butterfly network. Due to the reduced switching activity, it mitigates the impact of timing issues, making it suitable for highspeed operation. From behavioral model simulations with a 10-bit current-steering DAC, a linearity improvement in spurious-free dynamic range of about 4 dBc is obtained for 10% amplitude mismatch in the current sources, demonstrating the improvement in linearity without the use of pseudo-random control signals.
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| 28. |
- Morales Chacon, Oscar, 1985-, et al.
(författare)
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Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters
- 2022
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Ingår i: 2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES). - : IEEE. - 9788363578220 ; , s. 93-98
-
Konferensbidrag (refereegranskat)abstract
- In this paper a comparative analysis of single- and dual-phase-clocked latch-driver circuits aimed at current-steering (CS) digital-to-analog converters (DACs) is presented. The design metrics of power consumption, propagation and switching delay as well as their product are considered. Moreover, an alternative latch-driver is proposed to sustain low-power consumption with short switching-delay. A 65 nm CMOS process is used and the results are obtained from post-layout simulations. In the analysis, dual-phase-clocked circuits consume about 2.4 x more power consumption and report 5.9 x shorter switching-delay with respect to the single-phase-clocked circuits. The proposed latch-driver consumes about 1.6 x more power with maintained switching-delay as the dual-phase-clocked solutions that leads to a reduction in the power-delay product of 25% and the lowest power-switching-delay product in the supply range 0.8-1.2 V.
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| 29. |
- Morales Chacón, Oscar, 1985-
(författare)
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Studies on the Performance Bounds and Design of Current-Steering DACs
- 2022
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Digital-to-analog converters (DACs) are key building blocks in various applications including radar and wireless communications. With the exponential growth of data throughput in modern communication standards, e.g., fifthgeneration (5G), DACs has been pushed to achieve direct frequency synthesis in the GHz-range with channel bandwidths preferably beyond 1 GHz. Yet, higher frequency synthesis results in augmented power consumption, which can significantly impact the wireless network if multiple DACs are utilized, e.g., in massive multiple-input and multiple-output (MIMO) antenna systems with digital beamforming as well as in end-user’s handheld devices subject to a less prolonged battery life. Moreover, advances in digital signal processing and integrated-circuit fabrication, leading to reduced power consumption and cost as well as more flexibility in software-defined radio transmitters have motivated the displacement of analog/RF circuits to the digital domain. At the same time, driving the DACs to cover the millimeter- Wave (mm-Wave) spectrum, ranging between 30-300 GHz. In this work, high-speed DACs operating in the GHz-range with maintained low power consumption is addressed. The Nyquist-rate DAC is chosen due to its simple conversion approach to facilitate the generation of channel bandwidths in the GHz-range.A 10-bit current-steering (CS) Nyquist DAC realized in 65-nm CMOS is presented. The design is intended for low-complexity and power consumption while targeting high-speed operation with over 1 GHz channel bandwidth and maintained linearity. The binary-weighted architecture is considered to achieve straightforward digital-to-analog conversion. Next, a theoretical analysis to obtain the energy consumption bounds in CS DACs is presented. The analysis considers the digital, mixed-signal and analog power domains as well as the design corners of noise, speed and linearity. This is validated from reported measurement results in published CS DACs implemented in CMOS technology. Furthermore, design considerations with enhancement techniques are addressed. A digital switching scheme to avoid complementary switching transitions and counteract for timing errors is presented. The proposed scheme improves also the yield in linearity due to stochastic amplitude errors with reduced switching activity. Then, a comparative analysis of latch-drivers commonly implemented in CS DACs is realized. The comparison includes single- and dual-clocked latch-drivers and an alternative solution is proposed to reduce the switching-delay and power consumption.
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| 30. |
- Qazi, Fahad, et al.
(författare)
-
A/D Conversion for Software Defined Radio
- 2010
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Ingår i: Proceedings of the IEEE 6th Karlsruhe Workshop on Software Defined Radios 2010. ; , s. 70-76
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper we discuss possible variants of A/D conversion in multi-standard and pure software-defined radio (SDR) receiver architectures. The requirements for the ADC dynamic range and linearity are formulated for the contemporary personal and data-communication RF standards. Two implementation examples of a ADC in 90 nm and 65 nm CMOS are presented. These are a multi-bit first-order ADC aimed at baseband conversion and a one-bit second-order aimed at direct RF conversion, respectively. With limited channel filtering the performance achieved for the baseband ADC is shown to be sufficient. However, for the direct RF ADC the dynamic range and linearity requirements cannot be fully satisfied. The presented work can be considered a step ahead toward a successful implementation of the true SDR in the future.
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| 31. |
- Qazi, Fahad, et al.
(författare)
-
A/D Conversion for Software Defined Radio
- 2010
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Ingår i: Proceedings of the GigaHerz Symposium 2010. - Karlsruhe : Karlsruhe Institute of Technology. ; , s. 36-36, s. 70-76
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)
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| 32. |
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| 33. |
- Roy, Sajib, et al.
(författare)
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Ultra-low power FIR filter using STSC-CVL logic
- 2011
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Ingår i: 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011. - : IEEE. - 9781424490196 ; , s. 1-4
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- The paper shows the implementation of digital FIR filter using ultra-low power logic components. Source coupled logic is used and operated at sub-threshold region to achieve low power consumption while keeping a satisfactory output swing. The STSCL (sub-threshold source coupled logic) circuit is added with controllable voltage-level feature to minimize overall leakage current flow, including both gate leakage and sub-threshold. Seven-stage ring oscillators are implemented in CMOS, STSCL and our proposed logic at similar supply voltage to observe the differences with power consumption for the proposed technique came at nW range. Later on the FIR was design in both CMOS and proposed with measurement results shown in the paper. All measurements for are shown using 65 nm process technology, at a supply voltage of 0.5 V.
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| 34. |
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| 35. |
- Sadeghifar, Mohammad Reza, et al.
(författare)
-
A higher Nyquist-range DAC employing sinusoidal interpolation
- 2010
-
Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.
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| 36. |
- Sadeghifar, Mohammad Reza, et al.
(författare)
-
A survey of RF DAC Architectures
- 2010
-
Ingår i: Proceedings of the Swedish System On Chip Conference, SSOCC 2010.
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- A brief overview of different approaches to implement highfrequency,digital-to-analog converters (DACs), sometimes also referredto as radio-frequency DACs (RF DACs) or mixer DACs is given.Recently, there has been a fairly increased activity within this research field. RF CMOS processes have matured and enables a higher degree of integration with high-speed digital circuits at a more reasonable cost. Also, lately, some new advances have been reported which addresses the architectural-level design issues. These new advances include, for example, the implementation of high-speed, digital sigma-delta modulators to be used with RF DACs to further enable an increase of the output frequency of the DACs.This work presents a small survey on how RF DACs operate and in some sense how they can be implemented. We outline some different architectures and discuss the pros and cons of those.
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| 37. |
- Sadeghifar, Mohammad Reza, 1983-
(författare)
-
Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters
- 2019
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The network latency in fifth generation mobile technology (5G) will be around one millisecond which is much lower than in 4G technology. This significantly faster response time together with higher information capacity and ultra-reliable communication in 5G technology will pave the way for future innovations in a smart and connected society. This new 5G network should be built on a reasonable wireless infrastructure and 5G radio base-stations that can be vastly deployed. That is, while the electrical specification of a radio base-station in 5G should be met in order to have the network functioning, the size, weight and power consumption of the radio system should be optimized to be able to commercially deploy these radios in a huge network.As the number of antenna elements increases in massive multiple-input multiple-output based radios such as in 5G, designing true multi-band base-station radios, with efficient physical size, power consumption and cost in emerging cellular bands especially in mid-bands (frequencies up to 10~GHz), is becoming a challenge. This demands a hard integration of radio components; particularly the radio's digital application-specific integrated circuits (ASIC) with high-performance energy-efficient multi-band data converters.In this dissertation radio frequency digital-to-analog converter (RF DAC) and semi-digital finite-impulse response (FIR) filter digital-to-analog converter has been studied. Different techniques are used in these structures to improve the transmitter's overall performance.In the RF DAC part, a radio frequency digital-to-analog converter solution is presented, which is capable of monolithic integration into today's digital ASIC due to its digital-in-nature architecture, while fulfills the stringent requirements of cellular network radio base station linearity and bandwidth. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone and hence achieving output frequencies up to the sample rate.In the semi-digital FIR part, optimization problem formulation for semi-digital FIR digital-to-analog converter is investigated. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital Sigma-Delta modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in semi-digital FIR DAC optimization problem formulation. It is shown that hardware cost of the semi-digital FIR DAC, can be reduced by introducing flexible coefficient precision in filter optimization while the semi-digital FIR DAC is not over-designed either. Different use cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metric are used in different use cases of the optimization problem formulation and solved to find out the optimum set of analog FIR taps.Moreover, a direct digital-to-RF converter (DRFC) is presented in this thesis where a semi-digital FIR topology utilizes voltage-mode RF DAC cells to synthesize spectrally clean signals at RF frequencies. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital Sigma-Delta modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter. The RF output frequencies are synthesized by a configurable voltage-mode RF DAC solution with a high linearity performance.A compensation technique to cancel the code-dependent supply current variation in voltage-mode RF DAC for radio frequency direct digital frequency synthesizer is also presented in this dissertation and is studied analytically. The voltage-mode RF DAC and the compensation technique are mathematically modeled and system-level simulation is performed to support the analytical discussion.
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| 38. |
- Sundberg, Christel, et al.
(författare)
-
1-µm spatial resolution in silicon photon-counting CT detectors
- 2021
-
Ingår i: Journal of Medical Imaging. - : SPIE - International Society for Optical Engineering. - 2329-4302 .- 2329-4310. ; 8:6
-
Tidskriftsartikel (refereegranskat)abstract
- Purpose: Spatial resolution for current scintillator-based computed tomography (CT) detectors is limited by the pixel size of about 1 mm. Direct conversion photon-counting detector prototypes with silicon- or cadmium-based detector materials have lately demonstrated spatial resolution equivalent to about 0.3 mm. We propose a development of the deep silicon photon-counting detector which will enable a resolution of 1 ?? µ m , a substantial improvement compared to the state of the art. Approach: With the deep silicon sensor, it is possible to integrate CMOS electronics and reduce the pixel size at the same time as significant on-sensor data processing capability is introduced. A Gaussian curve can then be fitted to the charge cloud created in each interaction.We evaluate the feasibility of measuring the charge cloud shape of Compton interactions for deep silicon to increase the spatial resolution. By combining a Monte Carlo photon simulation with a charge transport model, we study the charge cloud distributions and induced currents as functions of the interaction position. For a simulated deep silicon detector with a pixel size of 12 ?? µ m , we present a method for estimating the interaction position. Results: Using estimations for electronic noise and a lowest threshold of 0.88 keV, we obtain a spatial resolution equivalent to 1.37 ?? µ m in the direction parallel to the silicon wafer and 78.28 ?? µ m in the direction orthogonal to the wafer. Conclusions: We have presented a simulation study of a deep silicon detector with a pixel size of 12 × 500 ?? µ m 2 and a method to estimate the x-ray interaction position with ultra-high resolution. Higher spatial resolution can in general be important to detect smaller details in the image. The very high spatial resolution in one dimension could be a path to a practical implementation of phase contrast imaging in CT.
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| 39. |
- Sundberg, Christel, et al.
(författare)
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Increasing the dose efficiency in silicon photon-counting detectors utilizing dual shapers
- 2018
-
Ingår i: Medical Imaging 2018. - : SPIE - International Society for Optical Engineering. - 9781510616363
-
Konferensbidrag (refereegranskat)abstract
- Silicon photon-counting spectral detectors are candidates for the next generation of medical CT. For silicon detectors, a low noise floor is necessary to obtain good detection efficiency. A low noise floor can be obtained by having a slow shaping filter in the ASIC, but this leads to a long dead-time, thus decreasing the count-rate performance. In this work, we evaluate the benefit of utilizing two sub-channels with different shaping times. It is shown by simulation that utilizing a dual shaper can increase the dose efficiency for equal count-rate capability by up to 17%.
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| 40. |
- Tan, Nianxiong, et al.
(författare)
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A CMOS digital-to-analog converter chipset for telecommunication
- 1997
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Ingår i: IEEE Circuits & Devices. - : IEEE. - 8755-3996 .- 1558-1888. ; 13:2, s. 11-16
-
Tidskriftsartikel (refereegranskat)abstract
- Describes a DAC chipset developed specifically for telecommunication applications. The DAC chipset is implemented in Ericsson's in-house 0.6-micron CMOS process and operates on a supply voltage ranging from 1.5 V to 5 V with the number of bits ranging from 10 to 14 bits, and data rate from 50 Msamples/s@1.5 V to over 100 Msamples/s@5 V
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| 41. |
- Tan, Nianxiong, et al.
(författare)
-
Differential Line Driver
- 1999
-
Patent (populärvet., debatt m.m.)abstract
- A fully differential line driver, especially for twisted copper pairs. It includes two current amplifiers made in standard CMOS technique, each having an input and an output, the latter being connected via terminal resistors to a voltage source, which may be set to a larger voltage than that used for driving the CMOS amplifiers. Accordingly, a low output impedance can be combined with a large swing. Further, feedback is not necessary, avoiding problems like potential instability. A very low-impedance input makes it appropriate for connecting to a DAC, thus reducing distortion of its output signal. The driver is suitable for very-high-speed-digital-subscriber-line modems.
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| 42. |
- Träff, Håkan, et al.
(författare)
-
Snapshot sampling for ultra-high speed data acquisition
- 1997
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Ingår i: Electronics Letters. - Herts, UK : The Institution of Engineering and Technology. - 0013-5194 .- 1350-911X. ; 33:13, s. 1137-1139
-
Tidskriftsartikel (refereegranskat)abstract
- A snapshot sampling technique is presented, which uses an optimised inverter chain for sample control and a simple sample-and-hold-circuit for highest speed and low current consumption. Simulations indicate a data acquisition time of 0.34 ns for a simple 0.8 μm digital CMOS process.
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| 43. |
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| 44. |
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| 45. |
- Wikner, Jacob, 1973-, et al.
(författare)
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D/A conversion interface design for DMT-ADSL applications
- 1998
-
Ingår i: IEEE Circuits & Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 8755-3996 .- 1558-1888. ; 14:6, s. 7-13
-
Tidskriftsartikel (refereegranskat)abstract
- For high-speed internet access, high-performance analog front-ends are needed, and data converters are one of the crucial building blocks in these bent-ends. In this article we will report on the modeling and design of a D/A conversion interface for a DMT (discrete multi tone)-based ADSL system that could be integrated into a complete CMOS analog front-end. We will discuss the DMT transmit spectrum and its impacts on data converters, we will focus on modeling and simulating of the whole D/A interface, and we will describe a test chip implemented in a 0.6 μm CMOS process
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| 46. |
- Wikner, Jacob, 1973-, et al.
(författare)
-
D/A Conversion Method and D/A Converter
- 2000
-
Patent (populärvet., debatt m.m.)abstract
- A D/A converter includes a triangular unit weight array. A decoder transforms digital samples into control signals having a linearly weighted binary representation. These control signal are used for activation/deactivation of entire rows or columns of the triangular unit weight array. Finally, the unit weights are combined into an analog output signal.
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| 47. |
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| 48. |
- Wikner, Jacob, 1973-, et al.
(författare)
-
Influence of Circuit Imperfections on the Performance of DACs
- 1999
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Ingår i: Analog Integrated Circuits and Signal Processing. - Hingham, MA, USA : Kluwer Academic Publishers. - 0925-1030 .- 1573-1979. ; 18:1, s. 7-20
-
Tidskriftsartikel (refereegranskat)abstract
- Digital-to-analog converters are crucial building blocks for telecommunication applications. For this kind of applications, the traditional static performance requirements do not apply. The dynamic performance is of the greatest importance. This paper discusses the aspects of the performance of CMOS digital-to-analog converters and models the influence of non-idealities of circuit components (such as output impedance, mismatch, circuit noise, etc.) on the frequency-domain performance. Both deterministic and stochastic effects are modeled. The purpose of this modeling is to provide an insightful design guide for high dynamic performance CMOS digital-to-analog converters.
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| 49. |
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| 50. |
- Wikner, Jacob, 1973-, et al.
(författare)
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Modeling of CMOS digital-to-analog converters for telecommunication
- 1999
-
Ingår i: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print). - : IEEE. - 1057-7130 .- 1558-125X. ; 46:5, s. 489-499
-
Tidskriftsartikel (refereegranskat)abstract
- This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance. Therefore, the characterization of the device and its performance is determined by frequency parameters such as the signal-to-noise ratio, spurious-free dynamic range, multitone power ratio, etc. In this paper, we show how these frequency-domain parameters are affected when mismatch errors and finite output impedance are applied to a current-steering CMOS DAC. We discuss how static performance is affected when changing the size of the errors and fundamental circuit parameters. The impact of dynamic errors such as glitches, slewing, and bit skew is discussed. Measurement results from 14-bit DACs are also shown to illustrate the correlation with the modeling.
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