| 1. |
- Rezaei, Amin, et al.
(författare)
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Efficient Congestion-Aware Scheme for Wireless On-Chip Networks
- 2016
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Ingår i: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467387767 ; , s. 742-749
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Konferensbidrag (refereegranskat)abstract
- Wireless NoC is becoming popular to be a promising future on-chip interconnection network as a result of high bandwidth, low latency and flexible topology configurations provided by this emerging technology. Nonetheless, congestion occurrence in wireless routers negatively affects the usability of high speed wireless links and considerably increases the network latency; therefore, in this paper, a congestion-aware platform (CAP-W) is introduced for wireless NoCs in order to reduce both internal and external congestions. The whole platform of CAP-W consists of an adaptive routing algorithm that balances utilization of wired and wireless networks, a dynamic task mapping approach that tries to minimize congestion probability, and a task migration strategy that considers dynamic variation of application behaviors. Simulation results show significant gain in congestion control over PEs of wireless NoC, compared to state-of-the-art works.
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| 2. |
- Savas, Suleyman, et al.
(författare)
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Generating hardware and software for RISC-V cores generated with Rocket Chip generator
- 2021
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Ingår i: Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021. - 2164-1676 .- 2164-1706. - 9781665429313 ; 2021-September, s. 89-94
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Konferensbidrag (refereegranskat)abstract
- This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow description of an algorithm as input and generates a combination of hardware (in Chisel) and software (in C) that interacts with the hardware. The hardware can be integrated with RISC-V cores created by the Rocket Chip generator and the software can be executed on these cores.The generated hardware requires similar amount of resources as the hand-written hardware while achieving equal or higher clock rates. As expected, the accelerators perform the calculations faster than the general purpose processor, 5 to 33x in our experiments. When these accelerators are integrated with the Rocket cores, they increase the performance by 25% and 260% in the two use-cases we investigate.
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