| 1. |
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| 2. |
- von Haartman, Martin, et al.
(författare)
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Random telegraph signal noise in SiGe heterojunction bipolar transistors
- 2002
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Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 92:8, s. 4414-4421
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Tidskriftsartikel (refereegranskat)abstract
- In this work, random telegraph signal (RTS) noise in SiGe heterojunction bipolar transistors (HBTs) was characterized both as a function of bias voltage and temperature. The RTS amplitudes were found to scale with the total base current, and the characteristic times in the higher and lower RTS state were found to decrease rapidly with bias voltage, approximately as 1/exp(qV(BE)/kT) or stronger. The RTS amplitudes were explained by a model based on voltage barrier height fluctuations across the base-emitter junction induced by trapped carriers in the space charge region. It was shown that the relative RTS amplitudes DeltaI(B)/I-B decrease exponentially with temperature in this model, which also was verified by measurements. The trapping/detrapping mechanism was suggested to be electron and hole capture, where the hole capture process occurs by tunneling. The characteristic times in both the lower and higher RTS state were in some cases found to decrease exponentially with temperature, characteristic for a thermally activated process, and in some cases found to be only weakly temperature dependent. The former behavior was explained by a multiphonon process with thermally activated capture cross sections, and an activation energy of 0.39 eV was extracted. RTS amplitudes proportional to the nonideal base current component or weaker were also found, originating from traps at the Si/SiO2 interface at the emitter periphery. The trapped carriers affect the recombination rate in the base-emitter space charge region, probably by changing the number of carriers. In this case, DeltaI(B)/I-B only showed a weak temperature dependence, which correlates well with this model. Characteristic times that decreased exponentially with temperature were observed, originating from a multiphonon process in the SiO2 with an activation energy for the capture cross section of 0.29 eV.
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| 3. |
- Hållstedt, Julius, et al.
(författare)
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Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels
- 2006
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:6, s. 466-468
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Tidskriftsartikel (refereegranskat)abstract
- The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.
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| 4. |
- Hållstedt, Julius, et al.
(författare)
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Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels
- 2006
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Ingår i: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. ; 3:7, s. 67-72
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Tidskriftsartikel (refereegranskat)abstract
- State of the art bulk and fully depleted SOI Si and SiGe channel pMOSFET devices with gate lengths ranging from 0.1 to 200 μm were fabricated and analyzed in terms of drain current drivability, mobility and noise performance. In general the SOI devices demonstrated superior mobility and significantly reduced I/f noise compared to bulk devices maintaining a well controlled short channel effects due to the ultra thin body.
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| 5. |
- Isheden, Christian, et al.
(författare)
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pMOSFETs with recessed and selectively regrown Si1-xGex source/drain junctions
- 2005
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Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 8:1-3, s. 359-362
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Tidskriftsartikel (refereegranskat)abstract
- A new source/drain formation concept based on selective Si etching followed by selective regrowth of in situ B-doped Si(1-x)Ge(x)is presented. Both process steps are performed in the same reactor to preserve the gate oxide. Well-behaved transistors are demonstrated with a negligibly low gate-to-substrate leakage current.
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| 6. |
- Malm, Bengt Gunnar, et al.
(författare)
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Influence of dislocations on low frequency noise in nMOSFETs fabricated on tensile strained virtual substrates
- 2007
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Ingår i: Noise and Fluctuations. - : AIP. - 9780735404328 ; , s. 133-136
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Konferensbidrag (refereegranskat)abstract
- In this work sSi nMOSFETs with 13 run sSi thickness on 27% Ge virtual substrates (VS) are investigated and an increased LF noise level with a characteristic gate bias dependence is found. High off-state leakage of the MOSFETs indicates the presence of misfit dislocations in the channel region. A channel conductance based model is proposed to analyse the noise originating from a highly localized defect in the channel.
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| 7. |
- Seger, Johan, et al.
(författare)
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Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator
- 2005
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 86:25
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Tidskriftsartikel (refereegranskat)abstract
- Lateral growth of Ni silicide towards the channel region of metal-oxide-semiconductor transistors (MOSFETs) fabricated on ultrathin silicon-on-insulator (SOI) is characterized using SOI wafers with a 20-nm-thick surface Si layer. With a 10-nm-thick Ni film for silicide formation, p-channel MOSFETs displaying ordinary device characteristics with silicided p(+) source/drain regions were demonstrated. No lateral growth of NiSix under gate isolation spacers was found according to electron microscopy. When the Ni film was 20 nm thick, Schottky contact source/drain MOSFETs showing typical ambipolar characteristics were obtained. A severe lateral encroachment of NiSix into the channel region leading to an increased gate leakage was revealed, while no detectable voiding at the silicide front towards the Si channel was observed.
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| 8. |
- von Haartman, Martin, et al.
(författare)
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1/f noise in Si and Si0.7Ge0.3 pMOSFETs
- 2003
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 50, s. 2513-2519
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Tidskriftsartikel (refereegranskat)abstract
- Strained layer Si0.7Ge0.3 pMOSFETs were fabricated and shown to exhibit enhanced hole mobility, up to 35% higher for a SiGe device with 3-nm-thick Si-cap, and lower 1/f noise compared to Si surface channel pMOSFETs. The 1/f noise in the investigated devices was dominated by mobility fluctuation noise and found to be lower in the SiGe devices. The source of the mobility fluctuations was determined by investigating the electric field dependence of the 1/f noise. It was found that the SiO2/Si interface roughness scattering plays an important role for the mobility fluctuation noise, although not dominating the effective mobility. The physical separation of the carriers from the SiO2/Si interface in the buried SiGe channel pMOSFETs resulted in lower SiO2/Si interface roughness scattering, which explains the reduction of 1/f noise in these devices. The 1/f noise mechanism was experimentally verified by studying 1/f noise in SiGe devices with various thicknesses of the Si-cap. A too large Si-cap thickness led to a deteriorated carrier confinement in the SiGe channel resulting in that considerable 1/f noise was generated in the parasitic current in the Si-cap. In our experiments, the SiGe devices with a Si-cap thickness in the middle of the interval 3-7 nm exhibited the lowest 1/f noise.
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| 9. |
- von Haartman, Martin, et al.
(författare)
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Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-κ gate dielectrics and TiN gate
- 2006
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 53:4, s. 836-846
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Tidskriftsartikel (refereegranskat)abstract
- Low-frequency noise and hole mobility are studied in Si and SiGe surface channel pMOSFETs with various types of high-kappa dielectric stacks (Al2O3, Al2O3/HfAlOx/Al2O3 and Al2O3/HfO2/Al2O3) and TiN as gate electrode material. Comparisons are made with poly-SiGe-gated pMOSFETs as well as P0lY-Si/SiO2/Si references. The choice of channel material (strained SiGe or Si), gate material (TiN or poly-SiGe), and high-kappa material (Al2O3, HfO2, HfAlOx) is discussed in terms of mobility and low-frequency noise. A TiN gate in combination with a surface SiGe channel is advantageous both for enhanced mobility and low 1/f noise. The dominant sources of carrier scattering are identified by analyzing the mobility measured at elevated temperatures. The 1/f noise is studied from subthreshold to strong inversion conditions and at different substrate biases. The mobility fluctuation noise model and the number fluctuation noise model are both used to investigate the 1/f-noise origin.
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| 10. |
- von Haartman, Martin, et al.
(författare)
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Effect of channel positioning on the 1/f noise in silicon-on-insulator metal-oxide-semiconductor field-effect transistors
- 2007
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Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 101:3
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Tidskriftsartikel (refereegranskat)abstract
- p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on silicon-on-insulator (SOI) substrates with an ultrathin (similar to 20 nm) lightly p-doped Si body were found to show about an order of magnitude lower 1/f noise than that in conventional bulk Si pMOSFETs when biased in strong inversion. In order to investigate the origin of the 1/f noise and find an explanation for the 1/f noise reduction, the 1/f noise in the SOI devices was studied as a function of the back gate voltage. The 1/f noise was found to increase with increasing back gate voltage, which acts to push the carriers closer towards the front gate oxide interface. The average distance of the inversion carriers from the gate oxide interface was obtained from simulations and used to interpret the 1/f noise behavior. The Hooge parameter, extracted for several different 1/f noise experiments where one or two terminal voltages were varied, exhibited a general behavior similar for both the SOI and bulk Si pMOSFETs. The Hooge parameter was shown to increase markedly when the average carrier-oxide separation is around 2 nm. Possible explanations of the results were discussed in terms of the mobility fluctuation noise model.
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| 11. |
- von Haartman, Martin, et al.
(författare)
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Influence of gate width on 50 nm gate length Si0.7Ge0.3 channel PMOSFETs
- 2003
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Ingår i: ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE. ; , s. 529-532
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Konferensbidrag (refereegranskat)abstract
- Compressively strained Si0.7Ge0.3 channel pMOSFETs were fabricated and the effective hole mobility was found to be 20-30% higher in the Si0.7Ge0.3 devices than in their Si counterparts. The g(m,) normalized to gate width, was found to increase strongly with decreasing gate width in the Si0.7Ge0.3 devices, a behavior that was not found in the Si devices. All the Si0.7Ge0.3 devices down to 50 nm gate length showed enhanced g. compared to the Si devices for gate widths <1 um. At L = 50 nm and W = 0.25 mum the Si0.7Ge0.3 devices exhibited increased g(m) and I-D of about 15 %, in saturation, compared to the Si devices. I-on was 286 muA/mum and I-off was 0.23 nA/mum at V-dd = 1.5 Vfor the Si0.7Ge0.3 device.
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| 12. |
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| 13. |
- von Haartman, Martin, et al.
(författare)
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Low-frequency noise and Coulomb scattering in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics
- 2005
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 49:6, s. 907-914
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Tidskriftsartikel (refereegranskat)abstract
- Carrier mobility and low-frequency noise were investigated in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics. The devices were annealed in H2O Vapor, which reduced the negative charge in the gate dielectrics. The carrier mobility was characterized versus change in oxide charge, which allowed an estimation of the Coulomb scattering from the charge in the Al2O3. The low-frequency noise was measured between subthreshold and strong inversion conditions in the H2O annealed and the un-annealed devices. The combined number fluctuation and correlated mobility fluctuation noise model could successfully explain the observed 1/f noise. The mobility fluctuations were negatively correlated to the number fluctuations in the un-annealed devices, which contained a negative oxide charge. In the H2O annealed devices, on the other hand, a positive correlation could be observed. The maximum magnitude of the scattering parameter a was found to be around 1 X 10(4) Vs/C. The H2O annealing was used in this work as a non-destructive tool to modify the charge in the Al2O3, but it can also be a viable method to improve device performance by introducing/passivating charge.
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| 14. |
- von Haartman, Martin, 1976-
(författare)
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Low-frequency noise characterization, evaluation and modeling of advanced Si- and SiGe-based CMOS transistors
- 2006
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static electrical measurements and low-frequency noise characterizations in this thesis. These novel field-effect transistors (FETs) include (i) compressively strained SiGe channel pMOSFETs, (ii) tensile strained Si nMOSFETs, (iii) MOSFETs with high-k gate dielectrics, (iv) metal gate and (v) silicon-on-insulator (SOI) devices. The low-frequency noise was comprehensively characterized for different types of operating conditions where the gate and bulk terminal voltages were varied. Detailed studies were made of the relationship between the 1/f noise and the device architecture, strain, device geometry, location of the conduction path, surface cleaning, gate oxide charges and traps, water vapour annealing, carrier mobility and other technological factors. The locations of the dominant noise sources as well as their physical mechanisms were investigated. Model parameters and physical properties were extracted and compared. Several important new insights and refinements of the existing 1/f noise theories and models were also suggested and analyzed. The continuing trend of miniaturizing device sizes and building devices with more advanced architectures and complex materials can lead to escalating 1/f noise levels, which degrades the signal-to-noise (SNR) ratio in electronic circuits. For example, the 1/f noise of some critical transistors in a radio receiver may ultimately limit the information capacity of the communication system. Therefore, analyzing electronic devices in order to control and find ways to diminish the 1/f noise is a very important and challenging research subject. We present compelling evidence that the 1/f noise is affected by the distance of the conduction channel from the gate oxide/semiconductor substrate interface, or alternatively the vertical electric field pushing the carriers towards the gate oxide. The location of the conduction channel can be varied by the voltage on the bulk and gate terminals as well by device engineering. Devices with a buried channel architecture such as buried SiGe channel pMOSFETs and accumulation mode MOSFETs on SOI show significantly reduced 1/f noise. The same observation is made when the substrate/source junction is forward biased which decreases the vertical electric field in the channel and increases the inversion layer separation from the gate oxide interface. A 1/f noise model based on mobility fluctuations originating from the scattering of electrons with phonons or surface roughness was proposed. Materials with a high dielectric constant (high-k) is necessary to replace the conventional SiO2 as gate dielectrics in the future in order to maintain a low leakage current at the same time as the capacitance of the gate dielectrics is scaled up. In this work, we have made some of the very first examinations of 1/f noise in MOSFETs with high-k structures composed by layers of HfO2, HfAlOx and Al2O3. The 1/f noise level was found to be elevated (up to 3 orders of magnitude) in the MOSFETs with high-k gate dielectrics compared to the reference devices with SiO2. The reason behind the higher 1/f noise is a high density of traps in the high-k stacks and increased mobility fluctuation noise, the latter possibly due to noise generation in the electron-phonon scattering that originates from remote phonon modes in the high-k. The combination of a TiN metal gate, HfAlOx and a compressively strained surface SiGe channel was found to be superior in terms of both high mobility and low 1/f noise.
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| 15. |
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| 16. |
- von Haartman, Martin, et al.
(författare)
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Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics
- 2004
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:12, s. 2271-2275
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Tidskriftsartikel (refereegranskat)abstract
- Low-frequency noise was characterized in Si0.7Ge0.3 surface channel pMOSFETs with ALD Al2O3/HfO2/Al2O3 stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al2O3 layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO2, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al2O3 layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.
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| 17. |
- von Haartman, Martin, et al.
(författare)
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Low-frequency noise in SiGe channel pMOSFETs on ultra-thin body SOI with Ni-silicided source/drain
- 2005
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Ingår i: Noise and Fluctuations. - : AIP. ; , s. 307-310
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Konferensbidrag (refereegranskat)abstract
- Thelow-frequency noise in buried SiGe channel pMOSFETs fabricated on ultra-thinbody silicon-on-insulator (SOI) substrates is investigated. The total thickness ofthe Si/SiGe/Si body structure, which is fully depleted (FD), is20 nm. The low-frequency noise properties are compared with FDSOI pMOSFETs with a 20 nm Si body. The effectof the Ni-silicide used in the Source/Drain were also studied,especially the case of Schottky-Barrier (SB) MOSFETs when the Ni-silicideis formed at the edges of the channel.
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| 18. |
- von Haartman, Martin, et al.
(författare)
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Noise in Si and SiGe MOSFETs with high-k gate dielectrics
- 2005
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Ingår i: Noise and Fluctuations. - : AIP. - 0735402671 ; , s. 225-230
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Konferensbidrag (refereegranskat)abstract
- This paper presents an overview of previous work and new insights on noise in Si-based MOSFETs with high-k gate dielectrics. Results for Al2O3, HfO2, HfAlOx and composite structures of these materials will be reported and compared. Incorporation of strained SiGe in high-k pMOSFETs in order to enhance hole mobility will be discussed in terms of low-frequency noise. A comparison will be made between devices with a surface Si channel, a surface SiGe channel and a buried SiGe channel. The influence of the gate electrode material and presence of a thin interfacial layer will be investigated. We will discuss noise modeling and highlight important differences compared to CMOS devices with standard gate oxide. Finally, we will discuss possible ways to reduce the 1/f noise in high-k MOSFETs. A noise reduction by a factor of two is obtained by forward biasing the substrate.
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| 19. |
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| 20. |
- Östling, Mikael, et al.
(författare)
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Critical technology issues for deca-nanometer MOSFETs
- 2007
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Ingår i: ICSICT-2006. - 1424401615 - 9781424401611 ; , s. 27-30
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Konferensbidrag (refereegranskat)abstract
- An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-K gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed.
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| 21. |
- Östling, Mikael, et al.
(författare)
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Device integration issues towards 10 nm MOSFETs
- 2006
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Ingår i: 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS. - NEW YORK, NY : IEEE. - 142440116X ; , s. 25-30
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Konferensbidrag (refereegranskat)abstract
- An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high K gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO(2)/Al(2)O(3). Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated, Finally ultra thin body Sol devices with high mobility SiGe channels are demonstrated.
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| 22. |
- Östling, Mikael, et al.
(författare)
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Novel integration concepts for sige-based rf-MOSFETs
- 2005
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Ingår i: Proc. Electrochem. Soc.. ; , s. 270-284
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Konferensbidrag (refereegranskat)abstract
- An overview of critical integration issues for future generation rf-MOSFETs is presented. The process requirements and implementation of selective epitaxy for the source and drain regions is given. In-situ doping of highly boron doped recessed SiGe S/D is demonstrated. Channel region engineering is discussed and 50 nm strained SiGe pMOSFETs are demonstrated. Implementation of high-κ gate dielectrics is presented and device performance is demonstrated for surface channel MOSFETs with a gate stack based on ALD-formed HfO2/Al 2O3. Low frequency noise properties for those devices are analyzed. Contact metallization issues are critical for ultra scaled devices and here the implementation of NiSi on SiGe(C) regions as well as on ultra thin body SOI MOSFETs are presented. Finally, a spacer pattering technology using optical lithography to fabricate sub-50 nm high-frequency MOSFETs is demonstrated.
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