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  • Schwarz, V., et al. (author)
  • 56 Gbit/s analogue PLL for clock recovery
  • 2001
  • In: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 37:22, s. 1336-1338
  • Journal article (peer-reviewed)abstract
    • A clock-recovery circuit is reported that employs a phase-locked. loop (PLL) at 56.88 Gbit/s. and is demonstrate by locking to a 28.44 GHz sinosoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences, To the knowledge of the authors, this is the First demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s.
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Type of publication
journal article (1)
Type of content
peer-reviewed (1)
Author/Editor
Willen, Bo G. (1)
Jackel, H. (1)
Schwarz, V. (1)
University
Royal Institute of Technology (1)
Language
English (1)
Year
2001 (1)

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