SwePub - sökning: onr:"swepub:oai:DiVA.org:kth-7...

Numrering	Referens	Omslagsbild	Hitta
1.	Hållstedt, Julius, et al. (författare) A robust spacer gate process for deca-nanometer high-frequency MOSFETs 2006 Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:3, s. 434-439 Tidskriftsartikel (refereegranskat)abstract This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

Hållstedt, Julius, et al. (författare)
A robust spacer gate process for deca-nanometer high-frequency MOSFETs
2006
Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:3, s. 434-439
Tidskriftsartikel (refereegranskat)abstract
- This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

Träfflista för sökning "onr:"swepub:oai:DiVA.org:kth-7507" "