| 11. |
- Al-Maqdasi, Zainab, 1986-, et al.
(författare)
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Conductive Regenerated Cellulose Fibers by Electroless Plating
- 2019
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Ingår i: Fibers. - Basel : MDPI. - 2079-6439. ; 7:5
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Tidskriftsartikel (refereegranskat)abstract
- Continuous metallized regenerated cellulose fibers for advanced applications (e.g. multi-functional composites) are produced by electroless copper plating. Copper is successfully deposited on the surface of cellulose fibers using commercial cyanide-free electroless copper plating package commonly available for manufacturing of printed wiring boards. The deposited copper is found to enhance the thermal stability, electrical conductivity and resistance to moisture uptake of the fibers. On the other hand, involved chemistry results in altering the molecular structure of the fibers as is indicated by the degradation of their mechanical performance (tensile strength and modulus).
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| 12. |
- Al-Maqdasi, Zainab, 1986-, et al.
(författare)
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Conductive Regenerated Cellulose Fibers for Multi-Functional Composites : Mechanical and Structural Investigation
- 2021
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Ingår i: Materials. - Basel, Switzerland : MDPI. - 1996-1944. ; 14:7
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Tidskriftsartikel (refereegranskat)abstract
- Regenerated cellulose fibers coated with copper via electroless plating process are investigated for their mechanical properties, molecular structure changes, and suitability for use in sensing applications. Mechanical properties are evaluated in terms of tensile stiffness and strength of fiber tows before, during and after the plating process. The effect of the treatment on the molecular structure of fibers is investigated by measuring their thermal stability with differential scanning calorimetry and obtaining Raman spectra of fibers at different stages of the treatment. Results show that the last stage in the electroless process (the plating step) is the most detrimental, causing changes in fibers’ properties. Fibers seem to lose their structural integrity and develop surface defects that result in a substantial loss in their mechanical strength. However, repeating the process more than once or elongating the residence time in the plating bath does not show a further negative effect on the strength but contributes to the increase in the copper coating thickness, and, subsequently, the final stiffness of the tows. Monitoring the changes in resistance values with applied strain on a model composite made of these conductive tows show an excellent correlation between the increase in strain and increase in electrical resistance. These results indicate that these fibers show potential when combined with conventional composites of glass or carbon fibers as structure monitoring devices without largely affecting their mechanical performance.
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| 13. |
- Aziz, Abdullah, 1992-, et al.
(författare)
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Distributed Digital Twins as Proxies-Unlocking Composability & Flexibility for Purpose-Oriented Digital Twins
- 2023
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Ingår i: IEEE Access. - : IEEE. - 2169-3536. ; 11, s. 137577-137593
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Tidskriftsartikel (refereegranskat)abstract
- In the realm of Industrial Internet of Things (IoT) and Industrial Cyber-Physical Systems (ICPS), Digital Twins (DTs) have revolutionized the management of physical entities. However, existing implementations often face constraints due to hardware-centric approaches and limited flexibility. This article introduces a transformative paradigm that harnesses the potential of distributed Digital Twins as proxies, enabling software-centricity and unlocking composability and flexibility for purpose-oriented digital twin development and deployment. The proposed microservices-based architecture, rooted in service-oriented architecture (SOA) and microservices principles, emphasizes reusability, modularity, and scalability. Leveraging the Lean Digital Twin Methodology and packaged business capabilities expedites digital twin creation and deployment, facilitating dynamic responses to evolving industrial demands. This architecture segments the industrial realm into physical and virtual spaces, where core components are responsible for digital twin management, deployment, and secure interactions. By abstracting and virtualizing physical entities into individual digital twins, this approach establishes the groundwork for purpose-oriented composite digital twin creation. Our key contributions involve a comprehensive exposition of the architecture, a practical proof-of-concept (PoC) implementation, and the application of the architecture in a use-case scenario. Additionally, we provide an analysis, including a quantitative evaluation of the proxy aspect and a qualitative comparison with traditional approaches. This assessment emphasizes key properties such as reusability, modularity, abstraction, discoverability, and security, transcending the limitations of contemporary industrial systems and enabling agile, adaptable digital proxies to meet modern industrial demands.
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| 14. |
- Bawankar, Nilesh, et al.
(författare)
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IoT-enabled Water Monitoring in Smart Cities with Retrofit and Solar-based Energy Harvesting
- 2024
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Ingår i: IEEE Access. - : IEEE. - 2169-3536. ; 12, s. 58222-58238
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Tidskriftsartikel (refereegranskat)abstract
- Monitoring water flow helps to identify leaks and wastage, leading to better management of water resources and conservation of this precious resource. To address this challenge, there is a need for an efficient and sustainable water management system. This paper presents an Internet of Things (IoT) based solution that involves retrofitting existing analog water meters using readily available off-the-shelf electronic components. Real-time data collection and analysis are performed through edge computation, which locally processes water meter images captured by the camera and extracts water meter readings. These readings are transmitted to the cloud for storage and further analysis. Various strategies have been implemented to optimize supply-current usage, preserving charge-discharge cycles of solar-powered batteries even in adverse environmental conditions. To streamline the firmware update process for multiple connected devices, a broadcasting technique is employed, offering the benefits of reduced manual labor and time savings. To assess the reliability and performance of developed solution, field deployment is conducted over several months, enabling the characterization of water usage patterns across different locations. Integrating energy harvesting capabilities into system reduces maintenance costs and promotes eco-friendly energy practices. Overall, this solution offers an effective and comprehensive approach towards achieving efficient and sustainable water management.
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| 15. |
- Bhoi, Bandan Kumar, et al.
(författare)
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Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit
- 2019
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Ingår i: VLSI Design and Test. - Singapore : Springer. - 9789813297661 ; , s. 34-46
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Konferensbidrag (refereegranskat)abstract
- Digital circuits need improvement in computation speed, reducing circuit complexity and power consumption. Emerging Technology NML can be such an architecture at nano-scale and thus emerges as a viable alternative for the digital CMOS VLSI. This technology has the capability to compute the logic as well as storage into the same device, which points out that it great potential for emerging technology. Since Nano-magnetic, technology fast approaches its minimal feature size, high device density and operate at room temperature. NML based circuits synthesis has to opt for novel half subtraction and Binary-to-Gray architecture for achieving minimal complexity and high-speed performance. This manuscript pro-poses area efficient binary half-subtraction and Binary-to-Gray converter architecture. Circuits’ synthesize are performed by MagCAD tool and simulate by Modelsim simulator. The circuit’s performance are estimated over other existing designs. The proposed converter consume 73.73%, and 94.49% less area than the converter designed using QCA and CMOS technique respectively. This is a significant contribution to this paper. Simulation results of converter show that the critical path delay falls within 0.15 µs.
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| 16. |
- Chouhan, Shailesh Singh, et al.
(författare)
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A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ◦C
- 2019
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Ingår i: Electronics. - : MDPI. - 2079-9292. ; 8:11
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Tidskriftsartikel (refereegranskat)abstract
- In this study, a temperature equivalent voltage signal was obtained by subtracting output voltages received from two individual temperature sensors. These sensors work in the subthreshold region and generate the output voltage signals that are proportional and complementary to the temperature. Over the temperature range of −40 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C to +85 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C without using any calibration method, absolute temperature inaccuracy less than ±0.6 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C was attained from the measurement of five prototypes of the proposed temperature sensor. The implementation was done in a standard 0.18 μ" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μ m CMOS technology with a total area of 0.0018 mm 2" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">2. The total power consumption is 40 nW for a supply voltage of 1.2 V measured at room temperature.
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| 17. |
- Imani, Roghayeh, et al.
(författare)
-
A Fully Additive Approach for the Fabrication of Split-Ring Resonator Metasurfaces
- 2022
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Ingår i: Proceedings: IEEE 72nd Electronic Components and Technology Conference (ECTC 2022). - : IEEE. - 9781665479431 ; , s. 1834-1840
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Metasurfaces, as a two-dimensional (2D) form of metamaterial, offer the possibility of designing miniaturized antennas for radio frequency (RF) energy harvesting systems with high efficiency, but fabrication of these antennas is still a major challenge. Printed circuit board (PCB) lithography, utilizing subtractive etch-and-print techniques to create metal interconnects on PCBs, was the first technique used to create metasurfaces antennas and remains the dominant technique to this day. The development of large-area fabrication techniques that are flexible, precise, uniform, cost-effective, and environmentally friendly is urgently needed for creating next-generation metasurfaces antenna. The present study reports a new fully additive manufacturing method for the fabrication of copper split-ring resonator (SRR) arrays on a PCB as a planar compact metasurfaces antenna. This new method was developed by combining sequential build up (SBU), laser direct writing (LDW), and covalent bonded metallization (CBM) methods and called (SBU-CBM). In this method, standard FR-4 covered with a layer of polyurethane was used as a basic PCB. The polymer surface was coated with a grafting molecule, followed by LDW to pattern the SRR array on the PCB. Finally, in electroless plating, only the laser-scanned area was selectively plated, and copper covalent bond metallization was selectively plated on the SRR pattern. Copper SRR arrays with different sizes were successfully fabricated on PCB using the SBU-CBM method. Copper strip lines within the SRR repeating building block were miniaturized up to 5 μm. To the best of our knowledge, this is the smallest size of a PCB antenna that has been reported to date.
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| 18. |
- Khan, Sajid, et al.
(författare)
-
A symmetric D flip-flop based PUF with improved uniqueness
- 2020
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Ingår i: Microelectronics and reliability. - : Elsevier. - 0026-2714 .- 1872-941X. ; 106
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Tidskriftsartikel (refereegranskat)abstract
- Physically unclonable functions (PUF) emerged as security primitives that generate high entropy, temper resilient bits for security applications. However, the implementation area budget limits their use in lightweight applications such as IoT, RFID, and biomedical applications. In the form of SRAM or D flip-flop, intrinsic PUFs are abundantly available in almost all of the designs. Being an integral part of the design, they can be used with compromised performance. In this work, to address the usage of intrinsic PUF, a D flip-flop based lightweight PUF is proposed. The proposed architecture is implemented on 40 nm CMOS technology. The simulation results show that it offers a uniqueness of 0.502 and the worst-case reliability of 95.89% at high temperature 125 °C and 97.89% at a supply voltage of 1.2 V. To evaluate the performance of various PUF architectures, A novel term, the uniqueness-to-reliability ratio, is proposed. When compared to the conventional D flip-flop, it offers 4.491 times more uniqueness and 127.74 times more uniqueness-to-reliability ratio with the same layout area. Since it uses the symmetrical structure, unlike other architectures, the proposed architecture does not require any post-processing schemes for bias removal, which further saves the silicon area. To verify the functional correctness of the simulation results, an FPGA implementation of the conventional and proposed D Flip-flop is also presented.
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| 19. |
- Khan, Sajid, et al.
(författare)
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An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications
- 2019
-
Ingår i: Microelectronics Journal. - : Elsevier. - 0959-8324 .- 0026-2692. ; 92
-
Tidskriftsartikel (refereegranskat)abstract
- Physically Unclonable Functions (PUF) have emerged as security primitives which can generate high entropy, temper resilient bits for security applications. However, the power budget of the ring oscillator (RO) PUF limits the use of RO PUF in IoT applications, in this concern a low power variant of RO PUF is much needed. In this paper, we have presented an ultra-low power, lightweight, configurable RO PUF based on the 4T XOR architecture. The proposed architecture is aging resilient; hence it produces a stable PUF output over the years. Also, it has a large number of challenge-response-pair (CRP) compared to the other architectures, which makes it suitable for chip identification as well as cryptographic key generation. The proposed PUF is implemented on 40 nm CMOS technology, and for the validation of design, we have also implemented on FPGA. The simulation results show that it has a uniqueness of 0.489 and worst-case reliability of 96.43% and 93.15% at 125 °C and 1.2 V, respectively. Compared to the conventional RO PUF it consumes 98.06% and 95.47% less dynamic and leakage power, respectively.
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| 20. |
- Khan, Sajid, et al.
(författare)
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D flip-flop based TRNG with zero hardware cost for IoT security applications
- 2021
-
Ingår i: Microelectronics and reliability. - : Elsevier. - 0026-2714 .- 1872-941X. ; 120
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Tidskriftsartikel (refereegranskat)abstract
- System-on-chips (SoCs) for the Internet of things (IoT) applications require hardware-based integrated random number generators for the secure transmission of information. However, they have limited hardware and power budget, which limits the use of on-chip dedicated True Random Number Generator (TRNG). In this work, a symmetric D flip-flop with integrated TRNG is proposed. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers good randomness with low energy-per-bit. In addition, the circuit has passed all the tests of NIST without any post-processing. When compared with the conventional D flip-flop, it has almost negligible area overhead that is only 0.14%. An FPGA implementation is also presented as a proof of concept that confirms the simulation results. Advanced Encryption Standard (AES) key expansion algorithm is also implemented to demonstrate the dual usage of the proposed D flip-flop.
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