| 1. |
- Liu, Ming, et al.
(författare)
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ATCA-based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments
- 2008
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Ingår i: 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2. ; , s. 287-292
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Konferensbidrag (refereegranskat)abstract
- An ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each Compute Node (CN) which appears as a Field Replaceable Unit (FRU) in an ATCA shelf, features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytes DDR2 memory. Connectivity is provided with 8 optical links and 5 Gigabit Ethernet ports, which are mounted on each board to receive data from detectors and forward results to outer shelves or PC farms with attached mass storage. Fast point-to-point on-board interconnections between FPGAs as well as the full-mesh shelf backplane provide flexibility and high bandwidth to partition algorithms and correlate results among them. The system represents a highly reconfigurable and scalable solution for multiple applications.
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| 2. |
- Liu, Ming, et al.
(författare)
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System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments
- 2008
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Ingår i: 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS. - LOS ALAMITOS : IEEE COMPUTER SOC. ; , s. 599-605
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Konferensbidrag (refereegranskat)abstract
- In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex algorithms are required for track recognition and reconstruction. This CPU-intensive task is usually implemented as off-line software running on PC clusters. In this paper we present a system-on-chip design for the track recognition and reconstruction based on modern FPGA technologies. The basic principle of the algorithm is polled from software into the FPGA fabric. The fundamental architecture of the tracking processor is described in detail. Working as processing engines in compute nodes, the tracking processor contributes to recognize potential track candidates in real-time and promotes the selection efficiency of the data acquisition and trigger system. Our design study shows that the tracking module can be integrated in a single Xilinx Virtex-4 FX60 FPGA. The processing capability of the design is about 16.7K sub-events per second per module with our experimental setup, which achieves 20 times speedup compared to the software implementation.
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| 3. |
- Lu, Zhonghai, et al.
(författare)
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Cluster-based simulated annealing for mapping cores onto 2D mesh networks on chip
- 2008
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Ingår i: 2008 IEEE Workshop On Design And Diagnostics Of Electronic Circuits And Systems, Proceedings. - 9781424422760 ; , s. 92-97
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Konferensbidrag (refereegranskat)abstract
- In Network-on-Chip (NoC) application design, core-to-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle the mapping problem in 2D mesh NoCs. In particular, we combine a clustering technique with the simulated annealing to speed up the convergence to near-optimal solutions. The clustering exploits the connectivity and distance relation in the network architecture as well as the locality and bandwidth requirements in the core communication graph. The annealing is cluster-aware and may be dynamically constrained within clusters. Our experiments suggest that simulated annealing can be effectively used to solve the mapping problem with a scalable size, and the combined strategy improves over the simulated annealing in execution time by up to 30% without compromising the quality of solutions.
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| 4. |
- She, Huimin, et al.
(författare)
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Deterministic Worst-case Performance Analysis for Wireless Sensor Networks
- 2008
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Ingår i: Proceedings of the International Wireless Communications and Mobile Computing Conference. - 9781424422029 ; , s. 1081-1086
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Konferensbidrag (refereegranskat)abstract
- Dimensioning wireless sensor networks requires formal methods to guarantee network performance and cost in any conditions. Based on network calculus, this paper presents a deterministic analysis method for evaluating the worst-case performance and buffer cost of sensor networks. To this end, we introduce three general traffic flow operators and derive their delay and buffer bounds. These operators are general because they can be used in combination to model any complex traffic flowing scenarios in sensor networks. Furthermore, our method integrates variable duty cycle to allow the sensor nodes to operate at lower rates thus saving power. Moreover, it incorporates traffic splitting mechanisms in order to balance network workload and nodes' buffers. To show how our method applies to real applications, we conduct a case study on a fresh food tracking application, which monitors the food freshness in realtime. The experimental results demonstrate that our method can be either used to perform network planning before deployment, or to conduct network reconfiguration after deployment.
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| 5. |
- Zhu, Jun, et al.
(författare)
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Energy efficient streaming applications with guaranteed throughput on MPSoCs
- 2008
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Ingår i: Proceedings of the 7th ACM International Conference on Embedded Software, EMSOFT 2008. - New York, NY, USA : ACM. - 9781605584683 ; , s. 119-128
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The public domain simulators Sim-Panalyzer and Cacti are used to estimate the energy dissipations of the parameterized architectural components. As the main contributions, we schedule the streaming applications on a multi-clock synchronous modeling framework, guarantee the application timing properties by throughput analysis, and customize both processor voltage-frequency levels and memory sizes in the design space to optimize the application pipeline parallelism for energy efficiency. Two widely used heuristic algorithms (i.e., greedy and taboo search) are used during the design optimization process. Our experiments show an energy reduction of 21% without any loss in application throughput compared with an ad-hoc approach.
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| 6. |
- Zhu, Jun, et al.
(författare)
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Performance Analysis of Reconfiguration in Adaptive Real-Time Streaming Applications
- 2008
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Ingår i: PROCEEDINGS OF THE 2008 IEEE/ACM/IFIP WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA. - 9781424426126 ; , s. 53-58
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Konferensbidrag (refereegranskat)abstract
- We propose a design optimization framework for adaptive real-time streaming applications. The main contribution is a hybrid approach for performance analysis combining formal analysis and simulation using a two-phase framework. We formulate the scheduling problem of adaptive streaming applications with ILP analysis, and use the simulation based on the synchronous model of computation to ensure throughput guarantees. We finally illustrate the capabilities of our methodology by experiments.
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