| 1. |
- Andersson, J. Y., et al.
(författare)
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SiGe/Si quantum structures as a thermistor material for low cost IR microbolometer focal plane arrays
- 2011
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 60:1, s. 100-104
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Tidskriftsartikel (refereegranskat)abstract
- Uncooled microbolometer thermal infrared detector technology is presently revolutionizing the infrared technology field. Essential improvement of the cost/performance ratio would be achieved by microbolometer arrays with higher sensitivity, since this allows the use of simpler and less costly camera optics, which implies a lower cost of the complete IR camera. The sensitivity of the microbolometers depends critically on the signal-to-noise ratio of the integrated thermistor material, which is set by its temperature coefficient of resistance (TCR) and noise characteristics. In this work we have investigated the use of epitaxial silicon-germanium/silicon (SiGe/Si) quantum well (QW) structures as a thermistor material. Si0.68Ge0.32/Si QW structures typically give a TCR of 3.0%/K and low noise values. A calculation of the noise equivalent temperature NETD of a bolometer gives 25 mK using the following assumptions: f-number = 1, 30 Hz video frame rate for a 640 x 480 array, with a pixel size 25 x 25 mu m. Higher TCR values are foreseen for SiGe/Si quantum dot structures, and the noise is expected to be similar to the QW based structures.
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| 2. |
- Dentoni Litta, Eugenio, et al.
(författare)
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Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology
- 2014
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 98, s. 20-25
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Tidskriftsartikel (refereegranskat)abstract
- This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.
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| 3. |
- Engström, Olof, 1943
(författare)
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Foreword
- 2010
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 54:2, s. 85-85
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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| 4. |
- Engström, Olof, 1943, et al.
(författare)
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Influence of interlayer properties on the characteristics of high-k gate stacks
- 2012
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 75, s. 63-68
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Tidskriftsartikel (refereegranskat)abstract
- The significance of interface sharpness between interlayers and high-k oxides for the properties of transistor gate-stacks has been investigated. Energy band variation in the oxide is calculated by using literature data for the HfO2/SiO2 interface, assuming two different cases for the interface plane: flat with a gradual depth variation of k-value and rough with an abrupt change of k. We demonstrate that the capacitive properties are similar, whereas tunneling properties considerably differ between the two cases. Furthermore, depth distributions of tunneling effective mass and dielectric constant have a substantial influence on the probability for charge carrier tunneling through the oxide stack and for the determination of capacitance equivalent oxide thickness (CET).
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| 5. |
- Farkas, Balazs, et al.
(författare)
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Flexible Thin-Flm Transistors on Planarized Parylene Substrate with Recessed Individual Backgates
- 2014
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 94, s. 11-14
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Tidskriftsartikel (refereegranskat)abstract
- With novel design and fabrication techniques, InGaZnO-based thin-film transistors with individual recessed back-gates were fabricated on flexible and transparent polymer substrates. The key components for the fabrication include using a machine park optimized for Si process technology, low-adhesion, room temperature parylene coating, AlOx–ZnOx(Al)-based inorganic lift-off process, and a recessed individual gate concept. Transistors were built to validate the viability of the design as well as aforementioned techniques. The demonstrated approach could open up new design possibilities for cheap, flexible devices, while the recessed-gate concept shows promise towards the use of more brittle layers in our flexible thin-film electronic devices.
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| 6. |
- Gudmundsson, Valur, et al.
(författare)
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Simulation of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo model
- 2013
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 79, s. 172-178
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Tidskriftsartikel (refereegranskat)abstract
- We present a simple and efficient approach to implement Schottky barrier contacts in a Multi-subband Monte Carlo simulator by using the subband smoothening technique to mimic tunneling at the Schottky junction. In the absence of scattering, simulation results for Schottky barrier MOSFETs are in agreement with ballistic Non-Equilibrium Green's Functions calculations. We then include the most relevant scattering mechanisms, and apply the model to the study of double gate Schottky barrier MOSFETs representative of the ITRS 2015 high performance device. Results show that a Schottky barrier height of less than approximately 0.15 eV is required to outperform the doped source/drain structure.
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| 7. |
- Henkel, Christoph, et al.
(författare)
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Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks
- 2012
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 74, s. 7-12
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Tidskriftsartikel (refereegranskat)abstract
- The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.
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| 8. |
- J T Simms, R J T, et al.
(författare)
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Micro-Raman spectroscopy as a voltage probe in AlGaN/GaN heterostructure devices: Determination of buffer resistances
- 2011
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Ingår i: SOLID-STATE ELECTRONICS. - : Elsevier Science B.V., Amsterdam.. - 0038-1101. ; 55:1, s. 5-7
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Tidskriftsartikel (refereegranskat)abstract
- A time-resolved micro-Raman technique was developed to probe the transient voltage in the GaN buffer layer of AlGaN/GaN heterostructure devices. The transient potential distribution under Ohmic contacts of devices behaved like a capacitance-resistance coupled network, with a decrease in amplitude and phase shift of the potential as a function of operating voltage frequency. This phenomenon was used to extract a value of 0.6 M Omega/square for sheet resistance of the AIN nucleation layer at the GaN/SiC interface from the characteristic RC value of the network. This demonstrates the effectiveness of this voltage probe technique as a non-invasive method of characterizing nucleation layers.
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| 9. |
- Jayakumar, Ganesh, et al.
(författare)
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Silicon nanowires integrated with CMOS circuits for biosensing application
- 2014
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 98, s. 26-31
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Tidskriftsartikel (refereegranskat)abstract
- We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.
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| 10. |
- Kaniewska, M, et al.
(författare)
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Charge carrier traffic at self-assembled Ge quantum dots on Si
- 2013
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 83, s. 99-106
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Tidskriftsartikel (refereegranskat)abstract
- Germanium quantum dots (QDs) have been characterized by deep level transient spectroscopy (DLTS) and capacitance versus voltage (C-V) technique. Two types of dots, grown by molecular beam epitaxy (MBE) at different temperatures, were investigated and assessed with respect to morphological properties. Samples with dots grown at 350 degrees C, were designed as n(++)-p-p(++) silicon junctions with the QDs positioned in the depleted p-region, while a second type of samples were Shottky diodes based on medium doped silicon with the QDs prepared at 550 degrees C and positioned in the Schottky depletion region. From the combined results of temperature scanned and frequency scanned DLTS, and by varying hole filling levels of the QD potentials, the energy distribution of states in the QD potentials were investigated. A wider distribution was found for the low-temperature QDs, probably related with a larger variation of size. By using a technique for separating tunneling and thermal hole emission, the average thermal activation energy for emitting holes to the valence band was found close to 0.40 eV for both types of QDs.
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