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Träfflista för sökning "L773:0038 1101 OR L773:1879 2405 srt2:(2005-2009)"

Sökning: L773:0038 1101 OR L773:1879 2405 > (2005-2009)

  • Resultat 1-10 av 26
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1.
  • Adnane, Bouchaib, et al. (författare)
  • Photoluminescence study of nanocrystalline-Si(Ge) embedded in mesoporous silica
  • 2009
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 53:8, s. 862-864
  • Tidskriftsartikel (refereegranskat)abstract
    • Photoluminescence (PL) properties of mesoporous silica (MS) samples incorporated with Si or Ge nanocrystals (nc) have been investigated with various excitation powers and post-RTA processes. The analysis of experimental results revealed a superlinear intensity dependence (m = 1.7) in the MS reference sample without nanocrystals, while a sublinear behavior (m = 0.8) is observed for the nc-Si in MS. It thus suggests the same recombination responsible for the luminescence at similar to 2.75 eV for both samples, but different kinetic limitations for the carrier transfer processes. Si nanocrystals play in this case an important role in generating more photo-excited carriers, enhancing the PL intensity.
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2.
  • Azam, Sher, et al. (författare)
  • Pulse Input Class-C Power Amplifier Response of SiC MESFET using Physical Transistor Structure in TCAD
  • 2008
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:5, s. 740-744
  • Tidskriftsartikel (refereegranskat)abstract
    • The switching behavior of a previously fabricated and tested SiC transistor is studied in Class-C amplifier in TCAD simulation. The transistor is simulated for pulse input signals in Class-C power amplifier. The simulated gain (dB), power density (W/mm) and power added efficiency (PAE%) at 500 MHz, 1, 2 and 3 GHz was studied using computational TCAD load pull simulation technique. A Maximum PAE of 77.8% at 500 MHz with 45.4 dB power gain and power density of 2.43 W/mm is achieved. This technique allows the prediction of switching response of the device for switching amplifier Classes (Class-C–F) before undertaking an expensive and time consuming device fabrication. The beauty of this technique is that, we need no matching and other lumped element networks for studying the large signal behavior of RF and microwave transistors.
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3.
  • Bengtsson, Olof, et al. (författare)
  • A Computational Load-Pull Method with Harmonic Loading for High-Efficiency Investigations
  • 2009
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 53:1, s. 86-94
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper a method for TCAD evaluation of RF-power transistors in high-efficiency operation using harmonic loading is presented. The method is based on large signal time-domain computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip-level. For method validation, a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency in class-F are identified by a comparative study to class-AB. Class-F harmonic termination is shown to give a 17% overall reduction of dissipated power and a 9% increase in output power. The expected efficiency increase is about 3–10% in the compression region depending on level of compression.
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4.
  • Bengtsson, Olof, et al. (författare)
  • Investigation of the non-linear input capacitance in LDMOS transistors and its contribution to IMD and phase distortion
  • 2008
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:7, s. 1024-1031
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1 dB compression point.
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5.
  • Ciechonski, Rafal, 1976-, et al. (författare)
  • Evaluation of MOS structures processed on 4H–SiC layers grown by PVT epitaxy
  • 2005
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 49:12, s. 1917-1920
  • Tidskriftsartikel (refereegranskat)abstract
    • MOS capacitors have been fabricated on 4H–SiC epilayers grown by physical vapor transport (PVT) epitaxy. The properties were compared with those on similar structures based on chemical vapor deposition (CVD) layers. Capacitance–voltage (C–V) and conductance measurements (G–V) were performed in the frequency range of 1 kHz to 1 MHz and also at temperatures up to 475 K. Detailed investigations of the PVT structures indicate a stable behaviour of the interface traps from room temperature up to 475 K. The amount of positive oxide charge QO is 6.83 × 109 cm−2 at room temperature and decreases with temperature increase. This suggests that the processed devices are temperature stable. The density of interface states Dit obtained by Nicollian–Brews conductance method is lower in the structure based on the PVT grown sample.
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6.
  • Driussi, F., et al. (författare)
  • On the electron mobility enhancement in biaxially strained Si MOSFETs
  • 2008
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:4, s. 498-505
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.
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7.
  • Echtermeyer, T., et al. (författare)
  • Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes
  • 2007
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 617-621
  • Tidskriftsartikel (refereegranskat)abstract
    • Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.
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8.
  • Engstrom, O., et al. (författare)
  • Navigation aids in the search for future high-k dielectrics : Physical and electrical trends
  • 2007
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 622-626
  • Tidskriftsartikel (refereegranskat)abstract
    • From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.
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9.
  • Gottlob, H. D. B., et al. (författare)
  • CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics
  • 2006
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 979-985
  • Tidskriftsartikel (refereegranskat)abstract
    • Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.
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10.
  • Johansson, Ted, et al. (författare)
  • Influence of SOI-generated stress on BiCMOS performance
  • 2006
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 935-942
  • Tidskriftsartikel (refereegranskat)abstract
    • Two BiCMOS processes were adapted for SOI and the performance of the bipolar devices was studied. Differences in electrical parameters were observed, in particular the current gain, which processing or doping profiles could not explain, but correlated with observed stress in transistors. Simulation of the process flow with stress included revealed that stress was generated to a higher degree in the SOI wafers in the presence of deep trench isolation (DTI). Theoretical estimations and electrical simulations with and without stress yielded results consistent with observed data. Thus, we conclude that the observed differences are caused by process-induced in-plane biaxial stress.
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  • Resultat 1-10 av 26

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