| 1. |
- Ayala, Christopher L., et al.
(författare)
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Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts
- 2015
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 113, s. 157-166
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Tidskriftsartikel (refereegranskat)abstract
- Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.
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| 2. |
- Chen, Tingsu, et al.
(författare)
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Integration of GMR-based spin torque oscillators and CMOS circuitry
- 2015
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 111, s. 91-99
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Tidskriftsartikel (refereegranskat)abstract
- This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm(2). The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies. (C) 2015 Elsevier Ltd. All rights reserved.
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| 3. |
- Dentoni Litta, Eugenio, et al.
(författare)
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Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs
- 2015
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 108, s. 24-29
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Tidskriftsartikel (refereegranskat)abstract
- High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.
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| 4. |
- Gnani, E., et al.
(författare)
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TFET inverter static and transient performances in presence of traps and localized strain
- 2019
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Ingår i: Solid-State Electronics. - : PERGAMON-ELSEVIER SCIENCE LTD. - 0038-1101 .- 1879-2405. ; 159, s. 38-42
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Tidskriftsartikel (refereegranskat)abstract
- This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different I-OFF values, namely 100 nA/mu m and 10 pA/mu m to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for I-OFF = 10 pA/mu m.
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| 5. |
- Kargarrazi, Saleh, et al.
(författare)
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A study on positive-feedback configuration of a bipolar SiC high temperature operational amplifier
- 2016
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Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 116, s. 33-37
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Tidskriftsartikel (refereegranskat)abstract
- This paper reports on the design and implementation of an integrated operational amplifier in bipolar SiC, and elaborates on its operation in positive-feedback configuration. The opamp is studied in different feedback setups: closed-loop compensated amplifier, comparator with hysteresis (Schmitt trigger), and as a relaxation oscillator. Measurement results suggest a stable closed-loop opamp with similar to 40 dB gain, a Schmitt trigger with constant threshold levels over a wide temperature range, and a relaxation oscillator tested up to 540 kHz. All the setups were tested from 25 degrees C up to 500 degrees C.
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| 6. |
- Khosa, Rabia Y., et al.
(författare)
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Electrical properties of 4H-SiC MIS capacitors with AlN gate dielectric grown by MOCVD
- 2019
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 153, s. 52-58
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Tidskriftsartikel (refereegranskat)abstract
- We report on the electrical properties of the AlN/4H-SiC interface using capacitance- and conductance-voltage (CV and GV) analysis of AlN/SiC MIS capacitors. The crystalline AlN layers are made by hot wall MOCVD. CV analysis at room temperature reveals an order of magnitude lower density of interface traps at the AlN/SiC interface than at nitrided SiO2/SiC interfaces. Electron trapping in bulk traps within the AlN is significant when the MIS capacitors are biased into accumulation resulting in a large flatband voltage shift towards higher gate voltage. This process is reversible and the electrons are fully released from the AlN layer if depletion bias is applied at elevated temperatures. Current-voltage (IV) analysis reveals that the breakdown electric field intensity across the AlN dielectric is 3–4 MV/cm and is limited by trap assisted leakage. By depositing an additional SiO2 layer on top of the AlN layer, it is possible to increase the breakdown voltage of the MIS capacitors significantly without having much impact on the quality of the AlN/SiC interface.
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| 7. |
- Olsson, Jörgen, 1966-, et al.
(författare)
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A New Latch-Free LIGBT on SOI with Very High Current Density and Low Drive Voltage
- 2016
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 115, s. 179-184
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Tidskriftsartikel (refereegranskat)abstract
- A new latch-free LIGBT on SOI is presented. The new device combines advantages from both LDMOS as well as LIGBT technologies; high breakdown voltage, high drive current density, low control voltages, at the same time eliminating latch-up problems. The new LIGBT has the unique property of independent scaling of the input control device, i.e. LDMOS, and the output part of the device, i.e. the p-n-p part. This allows for additional freedom in designing and optimizing the device properties. Breakdown voltage of over 200 V, on-state current density over 3 A/mm, specific on-resistance below 190 mWmm2, and latch-free operation is demonstrated.
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| 8. |
- Qin, Changliang, et al.
(författare)
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Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 14 nm node FinFETs
- 2016
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Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 124, s. 10-15
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Tidskriftsartikel (refereegranskat)abstract
- A complete mapping of 14 nm FinFETs performance over 200 mm wafers was performed and the pattern dependency of SiGe selective growth was calculated using an empirical kinetic molecule model for the reactant precursors. The transistor structures were analyzed by conventional characterization tools and their performance was simulated by considering the process related variations. The applied model presents for the first time a powerful tool for transistor community to predict the SiGe profile and strain modulating over a processed wafer, independent of wafer size.
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| 9. |
- Qin, Changliang, et al.
(författare)
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Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs
- 2016
-
Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 123, s. 38-43
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF2 in SiGe layers. The overlap space between doping junction and channel region has great effect on the device's performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer ID-VG curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on-off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.
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| 10. |
- Smith, Anderson D., et al.
(författare)
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Large scale integration of graphene transistors for potential applications in the back end of the line
- 2015
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 108, s. 61-66
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Tidskriftsartikel (refereegranskat)abstract
- A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm(2) V-1 s(-1). Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introduting graphene into wafer scale process lines.
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