| 1. |
- Alshebly, Wisam, et al.
(författare)
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Transcapacitances Modeling in ultra-thin gate-all-around junctionless nanowire FETs, including 2D quantum confinement
- 2023
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Ingår i: Solid-State Electronics. - : PERGAMON-ELSEVIER SCIENCE LTD. - 0038-1101 .- 1879-2405. ; 200
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Tidskriftsartikel (refereegranskat)abstract
- In this work, we propose an analytical model for the intrinsic transcapacitances in ultra-thin gate-all-around junctionless nanowire field effect transistors in the presence of confined energy states of electrons. The validity of the developed model is confirmed from deep depletion to accumulation and from linear to saturation, based on the numerical solution of the Schrodinger equation using Technology Computer Aided Design (TCAD) simulations. This represents an important stage toward AC small signal analysis of junctionless nanowire-based circuits.
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| 2. |
- Shafizadeh, Danial, et al.
(författare)
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Charge-based modeling of ultra narrow junctionless cylindrical nanowire FETs
- 2021
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Ingår i: Solid-State Electronics. - : PERGAMON-ELSEVIER SCIENCE LTD. - 0038-1101 .- 1879-2405. ; 185
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Tidskriftsartikel (refereegranskat)abstract
- This brief proposes an analytical approach to model the DC electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistors (JL-NW-FETs). The model includes explicit expressions, taking into account the first-order perturbation theory for calculating eigenstates and corresponding wave-functions obtained by the Schro center dot dinger equation in the cylindrical-coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step toward the analysis of circuits, mainly biosensors based on junctionless nanowire transistors.
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| 3. |
- Cherkaoui, K., et al.
(författare)
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High-k/InGaAs interface defects at cryogenic temperature
- 2023
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Ingår i: Solid-State Electronics. - 0038-1101. ; 207
-
Tidskriftsartikel (refereegranskat)abstract
- Oxide defects in the high-k/InGaAs MOS system are investigated. The behaviour of these traps is explored from room temperature down to 10 K. This study reveals that the exchange of free carriers between oxide states and either the conduction or the valence band is strongly temperature dependant. The capture and emission of electrons is strongly suppressed at 10 K as demonstrated by the collapse of the capacitance frequency dispersion in accumulation for n-InGaAs MOS devices, though hysteresis in the C-V sweeps is still present at 10 K. Phonon assisted tunnelling processes are considered in the simulation of electrical characteristics. The simulated data match very well the experimental characteristics and provide energy and spatial mapping of oxide defects. The multi phonon theory also help explain the impedance data temperature dependence. This study also reveals an asymmetry in the free carrier trapping between n and p type devices, where hole trapping is more significant at 10 K.
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| 4. |
- Hellenbrand, Markus, et al.
(författare)
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Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
- 2020
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 171
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Tidskriftsartikel (refereegranskat)abstract
- We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model alongside results from previous investigations of III-V RF MOSFETs and thus provide a comprehensive physical small-signal RF model for this type of transistor, which accurately describes the measured admittance parameters and gains. We verify the physical basis of the model assumptions by calculating the oxide defect density from the measured admittances.
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