| 1. |
- Garrido Gálvez, Mario
(författare)
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A New Representation of FFT Algorithms Using Triangular Matrices
- 2016
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 63:10, s. 1737-1745
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Tidskriftsartikel (refereegranskat)abstract
- In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.
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| 2. |
- Garrido Gálvez, Mario, et al.
(författare)
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Feedforward FFT Hardware Architectures Based on Rotator Allocation
- 2018
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 65:2, s. 581-592
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.
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| 3. |
- Garrido, Mario, 1981-, et al.
(författare)
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World’s Fastest FFT Architectures : Breaking the Barrier of 100 GS/s
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 66:4, s. 1507-1516
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The architectures are based on a fully parallel implementation of the FFT algorithm. In order to obtain the highest throughput while keeping the resource utilization low, we base our design on making use of advanced shift-and-add techniques to implement the rotators and on selecting the most suitable FFT algorithms for these architectures. Apart from high throughput and resource efficiency, we also guarantee high accuracy in the proposed architectures. For the implementation, we have developed an automatic tool that generates the architectures as a function of the FFT size, input word length and accuracy of the rotations. We provide experimental results covering various FFT sizes, FFT algorithms, and field-programmable gate array boards. These results show that it is possible to break the barrier of 100 GS/s for FFT calculation.
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| 4. |
- Huan, Yuxiang, et al.
(författare)
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A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications
- 2016
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 63:12, s. 2245-2256
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Tidskriftsartikel (refereegranskat)abstract
- Adapting the processor to the target application is essential in the Internet-of-Things (IoT), and thus requires customizability in order to improve energy efficiency and scalability to provide sufficient performance. In this paper, a reconfigurable and scalable control-centric architecture is proposed, and a processor consisting of two cores and an on-chip multi-mode router is implemented. Reconfigurability is enabled by a programmable sequence mapping table (SMT) which reorganizes functional units in each cycle, thus increasing hardware utilization and reducing excessive data movement for high energy efficiency. The router facilitates both wormhole and circuit switching to construct intra- or inter-chip interconnections, providing scalable performance. Fabricated in a 65-nm process, the chip exhibits 101.4 GOPS/W energy efficiency with a die size of 3.5 mm(2). The processor carries out general-purpose processing with a code size 29% smaller than the ARM Cortex M4, and improves the performance of application-specific processing by over ten times when implementing AES and RSA using SMTs instead of general-purpose C. By utilizing the on-chip router, the processor can be interconnected up to 256 nodes, with a single link bandwidth of 1.4 Gbps.
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| 5. |
- Ivanisevic, Nikola, et al.
(författare)
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A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
- 2018
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 05
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.
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| 6. |
- Jakobsson, Anders, et al.
(författare)
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Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS
- 2015
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE Computer Society. - 1549-8328 .- 1558-0806. ; 62:3, s. 680-688
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Tidskriftsartikel (refereegranskat)abstract
- A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 um CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.
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| 7. |
- Kanders, Hans, et al.
(författare)
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A 1 Million-Point FFT on a Single FPGA
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 66:10, s. 3863-3873
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present the first implementation of a 1 million-point fast Fourier transform (FFT) completely integrated on a single field-programmable gate array (FPGA), without the need for external memory or multiple interconnected FPGAs. The proposed architecture is a pipelined single-delay feedback (SDF) FFT. The architecture includes a specifically designed 1 million-point rotator with high accuracy and a thorough study of the word length at the different FFT stages in order to increase the signal-to-quantization-noise ratio (SQNR) and keep the area low. This also results in low power consumption.
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| 8. |
- Mohamad, Medhat, et al.
(författare)
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A Novel Transmitter Architecture for Spectrally-Precoded OFDM
- 2018
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 65:8, s. 2592-2605
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Tidskriftsartikel (refereegranskat)abstract
- Frequency nulling spectral precoding is an approachthat suppresses the out-of-band emission in OFDM systems.In this paper, we discuss the transmitter architecture of thespectrally precoded OFDM systems. We design a novel precoderthat matches the practical implementation of the OFDM modulator.We show that spectral precoding can relax the analog lowpass filtering requirements of the OFDM system transmitter. Weexamine the effect of spectral precoding on the PAPR as wellas the effect of the PA on the spectral precoding suppressionperformance. We also study the compliance of the spectrallyprecoded OFDM transmitter with the 3GPP standardizationmeasures and analyze its computation complexity. At the receiverside, we analyze the in-band interference and BER performanceof the suggested precoding approach.
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| 9. |
- Ojani, Amin, et al.
(författare)
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Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers
- 2015
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 62:1, s. 273-282
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Tidskriftsartikel (refereegranskat)abstract
- Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.
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| 10. |
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