| 1. |
- Agirre, J. A., et al.
(författare)
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The VALU3S ECSEL project : Verification and validation of automated systems safety and security
- 2021
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Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 87, s. 104349-
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Tidskriftsartikel (refereegranskat)abstract
- Manufacturers of automated systems and their components have been allocating an enormous amount of time and effort in R&D activities, which led to the availability of prototypes demonstrating new capabilities as well as the introduction of such systems to the market within different domains. Manufacturers need to make sure that the systems function in the intended way and according to specifications. This is not a trivial task as system complexity rises dramatically the more integrated and interconnected these systems become with the addition of automated functionality and features to them. This effort translates into an overhead on the V&V (verification and validation) process making it time-consuming and costly. In this paper, we present VALU3S, an ECSEL JU (joint undertaking) project that aims to evaluate the state-of-the-art V&V methods and tools, and design a multi-domain framework to create a clear structure around the components and elements needed to conduct the V&V process. The main expected benefit of the framework is to reduce time and cost needed to verify and validate automated systems with respect to safety, cyber-security, and privacy requirements. This is done through identification and classification of evaluation methods, tools, environments and concepts for V&V of automated systems with respect to the mentioned requirements. VALU3S will provide guidelines to the V&V community including engineers and researchers on how the V&V of automated systems could be improved considering the cost, time and effort of conducting V&V processes. To this end, VALU3S brings together a consortium with partners from 10 different countries, amounting to a mix of 25 industrial partners, 6 leading research institutes, and 10 universities to reach the project goal.
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| 2. |
- Batista, Gracieth Cavalcanti, et al.
(författare)
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Machine learning algorithm partially reconfigured on FPGA for an image edge detection system
- 2024
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Ingår i: Journal of Electronic Science and Technology. - : Elsevier BV. - 1674-862X. ; 22:2
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Tidskriftsartikel (refereegranskat)abstract
- Unmanned aerial vehicles (UAVs) have been widely used in military, medical, wireless communications, aerial surveillance, etc. One key topic involving UAVs is pose estimation in autonomous navigation. A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system (GNSS) signal. However, some factors can interfere with the GNSS signal, such as ionospheric scintillation, jamming, or spoofing. One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images. But a high effort is required for image edge extraction. In this paper, a support vector regression (SVR) model is proposed to reduce this computational load and processing time. The dynamic partial reconfiguration (DPR) of part of the SVR datapath is implementated to accelerate the process, reduce the area, and analyze its granularity by increasing the grain size of the reconfigurable region. Results show that the implementation in hardware is 68 times faster than that in software. This architecure with DPR also facilitates the low power consumption of 4 mW, leading to a reduction of 57% than that without DPR. This is also the lowest power consumption in current machine learning hardware implementations. Besides, the circuitry area is 41 times smaller. SVR with Gaussian kernel shows a success rate of 99.18% and minimum square error of 0.0146 for testing with the planning trajectory. This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application, thus contributing to lower power consumption, smaller hardware area, and shorter execution time.
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| 3. |
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| 4. |
- Ngo, Kalle
(författare)
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Side-Channel Analysis of Post-Quantum Cryptographic Algorithms
- 2023
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Public key cryptographic schemes used today rely on the intractability of certain mathematical problems that are known to be efficiently solvable with a large-scale quantum computer. To address the need for long-term security, in 2016 NIST started a project for standardizing post-quantum cryptography (PQC) primitives that rely on problems not known to be targets for a quantum computer, such as lattice problems. However, algorithms that are secure from the point of view of traditional cryptanalysis can be susceptible to side-channel attacks. Therefore, NIST put a major emphasis on evaluating the resistance of candidate algorithms to side-channel attacks.This thesis focuses on investigating the susceptibility of two NIST PQC candidates, Saber and CRYSTALS-Kyber Key Encapsulation Mechanisms (KEMs), to side-channel attacks. We present a collection of nine papers, of which eight focus on side-channel analysis of Saber and CRYSTALS-Kyber, and one demonstrates a passive side-channel attack on a hardware random number generator (RNG) integrated in STM32 MCUs.In the first three papers, we demonstrate attacks on higher-order masked software implementations of Saber and CRYSTALS-Kyber. One of the main contributions is a single-step deep learning message recovery method capable of recovering secrets from a masked implementation directly, without explicitly extracting the random masks. Another main contribution is a new neural network training method called recursive learning, which enables the training of neural networks capable of recovering a message bit with a probability higher than 99% from higher-order masked implementations.In the next two papers, we show that even software implementations of Saber and CRYSTALS-Kyber protected by both first-order masking and shuffling can be compromised. We present two methods for message recovery: Hamming weight-based and Fisher-Yates (FY) index-based. Both approaches are successful in recovering secret keys, with the latter using considerably fewer traces. In addition, we extend the ECC-based secret key recovery method presented in the prior chapter to ECCs with larger code distances.In the last two papers, we consider a different type of side channel amplitude-modulated electromagnetic (EM) emanations. We show that information leaked from implementations of Saber and CRYSTALS-Kyber through amplitude-modulated EM side channels can be used to recover the session and secret keys. The main contribution is a multi-bit error-injection method that allows us to exploit byte-level leakage. We demonstrate the success of our method on an nRF52832 system-on-chip supporting Bluetooth 5 and a hardware implementation of CRYSTALS-Kyber in a Xilinx Artix-7 FPGA.Finally, we present a passive side-channel attack on a hardware TRNG in a commercial integrated circuit in our last paper. We demonstrate that it is possible to train a neural network capable of recovering the Hamming weight of random numbers generated by the RNG from power traces with a higher than 60% probability. We also present a new method for mitigating device inter-variability based on iterative re-training.Overall, our research highlights the importance of evaluating the resistance of candidate PQC algorithm implementations to side-channel attacks and demonstrates the susceptibility of current implementations to various types of side channel analysis. Our findings are expected to provide valuable insights into the design of future PQC algorithms that are resistant to side-channel analysis.
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| 5. |
- Rajkumar, Trishna, et al.
(författare)
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A Markovian Approach for Detecting Failures in the Xilinx SEM core
- 2022
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Ingår i: FPT 2022. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- The soft error mitigation (SEM) core is an internal scrubber used to detect and correct single event upsets in the configuration memory. Although the core can mitigate errors with a high accuracy, recent studies have found it to be vulnerable to radiation errors owing to its implementation in the FPGA fabric. As the reliability of the system depends on the correctness of the scrubber, undetected SEM failure is hazardous in critical applications. In this study, we investigate the effectiveness of Markov chains in detecting such failures. In order to minimise the effects of single event upsets, the detection scheme is implemented external to the FPGA and leverages log analysis to monitor the SEM health. We evaluated our approach on the Xilinx ZCU104 Ultrascale+ board using fault injection. The results show that the SEM failures caused by single and double bit errors could be detected with an F_{1} score of 0.90 and 0.99 respectively. To the best of our knowledge, this is the first custom approach for failure detection in the SEM core.
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| 6. |
- Rajkumar, Trishna, et al.
(författare)
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AnoDe : A Log-based Self-Supervised Framework to Detect Scrubber Failures in SRAM-FPGA
- 2022
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Ingår i: 2022 IEEE 27TH PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING (PRDC). - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 164-171
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Konferensbidrag (refereegranskat)abstract
- SRAM-FPGAs used in radiative environment are integrated with a scrubber to protect the configuration memory from radiation effects. Any malfunctions in the scrubber degrades the reliability of the system and can have catastrophic consequences in critical applications. Existing solutions for a reliable scrubber focus on masking or detecting the scrubber errors through redundant modules implemented in the FPGA. While these approaches improve the overall reliability, they are not completely radiation-proof owing to their implementation on FPGA. In order to improve the scrubber reliability, a complementary scheme external to the FPGA is required. Based on this consideration, we propose AnoDe, a failure detection framework running on a supervisory processor external to the FPGA board. AnoDe leverages the logs generated by the scrubber to detect failures in real-time using an Autoencoder network. AnoDe provides a self-supervised solution right from generating the labelled training data to dynamically adapting to the prevailing radiation conditions. We evaluated the effectiveness of our approach on a Xilinx Ultrascale+ MPSoC ZCU104 board using fault injection. The results demonstrated a detection performance comparable to that of a custom approach with an F1 score of 0.85 for single bit upsets and 0.93 for multi bit upsets. Overall, the proposed approach could reduce the scrubber SEU sensitivity from 6 % to 1 %.
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| 7. |
- Trujilho, Leandro, et al.
(författare)
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Dependable I2C Communication with FPGA
- 2022
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Ingår i: PROCEEDINGS OF THE 7TH BRAZILIAN TECHNOLOGY SYMPOSIUM (BTSYM'21). - Cham : Springer Nature. ; , s. 383-395
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Konferensbidrag (refereegranskat)abstract
- This work introduces the I2C bus availability problem for Cube Satellites and robotics applications. It suggests the use of FPGAs as an alternative to microcontroller systems as they are capable of recovering from bus faults via partial reconfiguration without mission interruption, and triple wire redundancy is feasible because more pins are available. The proposed topology makes use of 3 AXI IIC IP core instances, a TMR voter, and a comparator along with a watchdog timer to detect faults and recover from them. The bus successfully recovered from fault injections instantly with IIC resets and after 17 ms via partial reconfiguration, occupying 5% of the LUTs, 1% of the LUTRAMs, 3% of Flip Flops and IO, consuming 1.684W with a total of 2.43% essential bits.
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