| 1. |
- Ekström, Mattias, et al.
(författare)
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Integration and High-Temperature Characterization of Ferroelectric Vanadium-Doped Bismuth Titanate Thin Films on Silicon Carbide
- 2017
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Ingår i: Journal of Electronic Materials. - : SPRINGER. - 0361-5235 .- 1543-186X. ; 46:7, s. 4478-4484
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Tidskriftsartikel (refereegranskat)abstract
- 4H-SiC electronics can operate at high temperature (HT), e.g., 300A degrees C to 500A degrees C, for extended times. Systems using sensors and amplifiers that operate at HT would benefit from microcontrollers which can also operate at HT. Microcontrollers require nonvolatile memory (NVM) for computer programs. In this work, we demonstrate the possibility of integrating ferroelectric vanadium-doped bismuth titanate (BiTV) thin films on 4H-SiC for HT memory applications, with BiTV ferroelectric capacitors providing memory functionality. Film deposition was achieved by laser ablation on Pt (111)/TiO2/4H-SiC substrates, with magnetron-sputtered Pt used as bottom electrode and thermally evaporated Au as upper contacts. Film characterization by x-ray diffraction analysis revealed predominately (117) orientation. P-E hysteresis loops measured at room temperature showed maximum 2P (r) of 48 mu C/cm(2), large enough for wide read margins. P-E loops were measurable up to 450A degrees C, with losses limiting measurements above 450A degrees C. The phase-transition temperature was determined to be about 660A degrees C from the discontinuity in dielectric permittivity, close to what is achieved for ceramics. These BiTV ferroelectric capacitors demonstrate potential for use in HT NVM applications for SiC digital electronics.
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| 2. |
- Ekström, Mattias, et al.
(författare)
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Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing
- 2018
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Ingår i: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017. - : Trans Tech Publications. - 9783035711455 ; , s. 389-392
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Konferensbidrag (refereegranskat)abstract
- Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.
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| 3. |
- Elahipanah, Hossein, et al.
(författare)
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4.5-kV 20-mΩ. cm2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension
- 2015
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Ingår i: Materials Science Forum. - : Trans Tech Publications Ltd. - 0255-5476 .- 1662-9752. - 9783038354789 ; 821, s. 838-841
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Tidskriftsartikel (refereegranskat)abstract
- A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.
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| 4. |
- Elahipanah, Hossein, et al.
(författare)
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5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension
- 2015
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Ingår i: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 36:2, s. 168-170
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Tidskriftsartikel (refereegranskat)abstract
- Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.
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| 5. |
- Elahipanah, Hossein, 1982-, et al.
(författare)
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500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits
- 2017
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Ingår i: IEEE Electron Device Letters. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0741-3106 .- 1558-0563.
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Tidskriftsartikel (refereegranskat)abstract
- High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.
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| 6. |
- Elahipanah, Hossein, et al.
(författare)
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A wafer-scale Ni-salicide contact technology on n-type 4H-SiC
- 2017
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Ingår i: ECS Journal of Solid State Science and Technology. - : Electrochemical Society. - 2162-8769 .- 2162-8777. ; 6:4, s. P197-P200
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Tidskriftsartikel (refereegranskat)abstract
- A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.
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| 7. |
- Elahipanah, Hossein, 1982-, et al.
(författare)
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A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC
- 2017
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Ingår i: ECS Journal of Solid State Science and Technology. - : ECS. - 2162-8769 .- 2162-8777. ; 6:4, s. 197-200
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Tidskriftsartikel (refereegranskat)abstract
- A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.
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| 8. |
- Elahipanah, Hossein, 1982-
(författare)
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Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors
- 2017
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- 4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development.To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized.Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process.Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated.This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.
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| 9. |
- Elahipanah, Hossein, et al.
(författare)
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Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors
- 2016
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 63:11, s. 4366-4372
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Tidskriftsartikel (refereegranskat)abstract
- A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H–SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.
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| 10. |
- Elahipanah, Hossein, et al.
(författare)
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Modification of etched junction termination extension for the high voltage 4H-SiC power devices
- 2016
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Ingår i: Silicon Carbide and Related Materials. - : Trans Tech Publications. - 9783035710427 ; , s. 978-981
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Konferensbidrag (refereegranskat)abstract
- High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) were fabricated and optimized in terms of the length (LJTE) and remaining dose (DJTE) of JTEs. It is found that for a given total termination length (Σ LJTEi), a decremental JTE length from the innermost edge to the outermost mesa edge of the device will result in better modification of the electric field. A breakdown voltage (BV) of 4.95 kV is measured for the modified device which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches were fabricated. The maximum current gain of 40 is achieved for a single finger device with the emitter width of 40 μm at IC = 0.25 A (JC = 310 A/cm2) which corresponds to RON = 33 mΩ.cm2. It is presented that the current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.
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