| 1. |
- Hou, Shuoben, et al.
(författare)
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A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C
- 2020
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Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 8:1, s. 116-121
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Tidskriftsartikel (refereegranskat)abstract
- An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.
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| 2. |
- Abedin, Ahmad, 1984-
(författare)
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Germanium layer transfer and device fabrication for monolithic 3D integration
- 2021
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. On the one hand, the scaling of devices isreaching critical dimensions, which makes their further downscaling techno-logically difficult and economically challenging, whereas, on the other hand,the field of electronics is no longer limited only to developing circuits thatare meant for data processing. Sensors, processors, actuators, memories, andeven power storage units need to be efficiently integrated into a single chip tomake IoT work. M3D integration through stacking different layers of deviceson each other can potentially improve circuits’ performance by shorteningthe wiring length and reducing the interconnect delay. Using multiple tiersfor device fabrication makes it possible to integrate different materials withsuperior physical properties. It offers the advantage of fabricating higher-performance devices with multiple functionalities on a single chip. However,high-quality layer transfer and processing temperature budget are the majorchallenges in M3D integration. This thesis involves an in-depth explorationof the application of germanium (Ge) in monolithic 3D integration.Ge has been recognized as one of the most promising materials that canreplace silicon (Si) as the channel material for p-type field-effect transistors(pFETs) because of its high hole mobility. Ge pFETs can be fabricated atsubstantially lower temperatures compared to Si devices which makes theformer a good candidate for M3D integration. However, the fabrication ofhigh-quality Ge-on-insulator (GOI) layers with superior thickness homogene-ity, low residual doping, and a sufficiently good interface with buried oxide(BOX) has been challenging.This thesis used low-temperature wafer bonding and etch-back techniquesto fabricate the GOI substrate for M3D applications. For this purpose, aunique stack of epitaxial layers was designed and fabricated. The layer stackcontains a Ge strain relaxed buffer (SRB) layer, a SiGe layer to be used asan etch stop, and a top Ge layer to be transferred to the handling wafer.The wafers were bonded at room temperature, and the sacrificial wafer wasremoved through multiple etching steps leaving 20 nm Ge on the insulatorwith excellent thickness homogeneity over the wafer. Ge pFET devices werefabricated on the GOI substrates and electrically characterized to evaluatethe layer quality. Finally, the epitaxial growth of the highly doped SiGeand sub-nm Si cap layers have been investigated as alternatives for improvedperformance Ge pFETs.The Ge buffer layer was developed through the two-step deposition tech-nique resulting in defect density of107cm−3and surface roughness of 0.5 nm.The fully strainedSi0.5Ge0.5film with high crystal quality was epitaxiallygrown at temperatures below 450°C. The layer was sandwiched between theGe buffer and the top 20 nm Ge layer to be used as an etch-stop in the etch- back process. A highly selective etching method was developed to remove the3μm Ge buffer and 10nm SiGe film without damaging the 20 nm transferringGe layer.The Ge pFETs were fabricated at temperatures below 600°C so that theycould be compatible with the M3D integration. The back interface of thedevices depleted atVBG= 0V, which confirmed the small density of fixedcharges at the Ge/BOX interface along with a low level of residual doping inthe Ge channel. The Ge pFETs with 70 % yield over the whole wafer showed60 % higher carrier mobility than Si reference devices.Low-temperature epitaxial growth of Si passivation layer on Ge was de-veloped in this thesis. For electrical evaluation of the passivation layer,metal-oxide-semiconductor (MOS) capacitors were fabricated and character-ized. The capacitors showed an interface trap density of3×1011eV−1cm−2,and hysteresis as low as 3 mV at Eox of 4MV/cm corresponding to oxide trapdensity of1.5×1010cm−2. The results indicate that this Si passivation layersubstantially improves the gate dielectric by reducing the subthreshold slopeof Ge devices while increasing their reliability. The in-situ doped SiGe layerwith a dopant concentration of2.5×1019cm−3and resistivity of 3.5 mΩcmwas selectively grown on Ge to improve the junction formation.The methods developed in this thesis are suitable for large-scale M3Dintegration of Ge pFET devices on the Si platform. The unique Ge layertransfer and etch-back techniques resulted in the fabrication of GOI substrateswith high thickness homogeneity, low residual doping, and sufficiently goodGe/BOX interface. The process temperatures for Ge transfer and pFETsfabrication are kept within the range of the M3D budget. Integration of theSi cap for gate dielectric formation and SiGe layers in the source/drain regionmay increase device performance and reliability
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| 3. |
- Bask, Mikael, 1967-, et al.
(författare)
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Language Tone in Financial News Media and the Cross-Section of Stock Returns
- 2020
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- Based on 58,256 news articles published in the Financial Times during a 15-year period that cover companies in the DJIA, we find that a trading strategy that longs stocks with the most negative news and shorts stocks with the least negative news is not profitable. Consistent with this result, we also find that the sentiment factor derived from the negativism in the language tone in news articles is not a priced risk factor in the cross-section of stock returns. Nevertheless, the sentiment factor is significant for two-thirds of the stocks when it is added to well-known factor models.
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| 4. |
- Bask, Mikael, 1967-, et al.
(författare)
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Media sentiment and stock returns
- 2024
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Ingår i: Quarterly Review of Economics and Finance. - : Elsevier. - 1062-9769 .- 1878-4259. ; 94, s. 303-311
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Tidskriftsartikel (refereegranskat)abstract
- Based on 35,344 news articles published in the Financial Times that cover 40 companies that have been included in the Dow Jones Industrial Average, we find that a negative media sentiment in the form of a negative language tone in news articles is a priced factor in five of nine asset-pricing models that aim to explain the cross-section of stock returns. In particular, the sentiment factor is a priced factor in the market model augmented with the sentiment factor in all three samples-the 2005-09 subsample, the 2010-18 subsample, and the 2005-18 full sample-and in the Fama-French three- and five-factor models augmented with the sentiment factor in the 2010-18 subsample. In addition, factor-spanning regressions with the Fama-French five-factor model as the right-hand-side model confirm that the sentiment factor contributes to the model's explanation of the stocks' mean excess returns in the 2005-09 subsample and the 2005-18 full sample.
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| 5. |
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| 6. |
- Fan, Xuge, et al.
(författare)
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Manufacture and characterization of graphene membranes with suspended silicon proof masses for MEMS and NEMS applications
- 2020
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Ingår i: MICROSYSTEMS & NANOENGINEERING. - : NATURE PUBLISHING GROUP. - 2055-7434. ; 6:1
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Tidskriftsartikel (refereegranskat)abstract
- Graphene's unparalleled strength, chemical stability, ultimate surface-to-volume ratio and excellent electronic properties make it an ideal candidate as a material for membranes in micro- and nanoelectromechanical systems (MEMS and NEMS). However, the integration of graphene into MEMS or NEMS devices and suspended structures such as proof masses on graphene membranes raises several technological challenges, including collapse and rupture of the graphene. We have developed a robust route for realizing membranes made of double-layer CVD graphene and suspending large silicon proof masses on membranes with high yields. We have demonstrated the manufacture of square graphene membranes with side lengths from 7 mu m to 110 mu m, and suspended proof masses consisting of solid silicon cubes that are from 5 mu mx5 mu mx16.4 mu m to 100 mu mx100 mu mx16.4 mu m in size. Our approach is compatible with wafer-scale MEMS and semiconductor manufacturing technologies, and the manufacturing yields of the graphene membranes with suspended proof masses were >90%, with >70% of the graphene membranes having >90% graphene area without visible defects. The measured resonance frequencies of the realized structures ranged from tens to hundreds of kHz, with quality factors ranging from 63 to 148. The graphene membranes with suspended proof masses were extremely robust, and were able to withstand indentation forces from an atomic force microscope (AFM) tip of up to 7000nN. The proposed approach for the reliable and large-scale manufacture of graphene membranes with suspended proof masses will enable the development and study of innovative NEMS devices with new functionalities and improved performances.
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| 7. |
- Garidis, Konstantinos, 1984-
(författare)
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Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration
- 2020
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- As the semiconductor industry moves beyond the 10 nm node, power consumption constraints and reduction of the negative impact of parasitic elements become important. Silicon germanium (Si1−xGex) alloys have been used to amplify the performance of Si based devices and integrated circuits (ICs) for decades. Selective epitaxial growth of heavily doped Si and/or Si1−xGex is commonly employed to reduce the effect of parasitic resistance. Reducing the supply voltage leads to lower dynamic power consumption in complementary metal-oxide-semiconductor (CMOS) technology. Monolithic three-dimensional integration (M3D) is a technology that employs vertical stacking of the device tiers. This approach reduces the wiring length, effectively reducing interconnect delay, load capacitance and ultimately reducing the power consumption. Among the integration challenges M3D is facing, one can distinguish the available thermal budget for fabrication, the crystalline quality of the device active layer and finally the actual device or circuit performance.Germanium channel devices can benefit M3D integration. Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated at significantly lower temperatures than Si. In addition, they potentially can have higher performance compared to Si due to the superior electron and hole mobilities of Ge. Active layer transfer of crystalline quality layers is a key step in a M3D fabrication flow. Direct wafer bonding techniques offerthe possibility to transfer a Ge layer on a patterned wafer. This thesis studies the various applications of Si1−xGex films in M3D. An initial implementation of an in situ doped Si1−xGex film on silicon-on-insulator (SOI) and germanium substrates is first presented. A Si1−xGex film isgrown selectively on SOI substrates to be used as a contact electrode on Si nanowire biosensors. On Ge bulk substrates, in situdoped Si1−xGex is epitaxially grown to form p+-n junctions. The junction leakage current and the mechanisms at play are studied. The analysis ofthe junction performance provides insights on the junction leakage mechanisms,an important issue for the implementation of in situ doped Si1−xGex in M3D. A low temperature germanium-on-insulator (GOI) fabrication flow based on room temperature wafer bonding and etch back is presented in this work. The method suggested in the thesis produces high quality, crystalline Ge device layers with excellent uniformity. The thesis also reports on the development and integration of Si1−xGex in the GOI fabrication as an etch stop layer, enabling the stability of the layer transfer process. Finally this thesis presents Ge p-channel field-effect transistor (PFET) devices fabricated on the previously developed GOI substrates.The technologies presented in this thesis can be integrated in large scale Ge device fabrication. The low temperature GOI and Ge PFET fabrication methods are very well suited for sequential device fabrication. The processes and applications presented in this thesis meet the current thermal budget, device performance and active layer transfer demands for M3D technology.
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| 8. |
- Garidis, Konstantinos, et al.
(författare)
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Selective epitaxial growth of in situ doped SiGe on bulk Ge for p+/n junction formation
- 2020
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Ingår i: Electronics. - : MDPI AG. - 2079-9292. ; 9:4
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Tidskriftsartikel (refereegranskat)abstract
- Epitaxial in situ doped Si0.73Ge0.27 alloys were grown selectively on patterned bulk Ge and bulk Si wafers. Si0.73Ge0.27 layers with a surface roughness of less than 3 nm were demonstrated. Selectively grown p+Si0.73Ge0.27 layers exhibited a resistivity of 3.5 mΩcm at a dopant concentration of 2.5 × 1019 boron atoms/cm3. P+/n diodes were fabricated by selectively growing p+-Si0.73Ge0.27 on n-doped bulk Ge and n-doped Si wafers, respectively. The geometrical leakage current contribution shifts from the perimeter to the bulk as the diode sizes increase. Extracted near midgap activation energies are similar to p+/n Ge junctions formed by ion implantation. This indicates that the reverse leakage current in p+/n Ge diodes fabricated with various doping methods, could originate from the same trap-assisted mechanism. Working p+/n diodes on Ge bulk substrates displayed a reverse current density as low as 2.2·10−2 A/cm2 which was found to be comparable to other literature data. The layers developed in this work can be used as an alternative method to form p+/n junctions on Ge substrates, showing comparable junction leakage results to ion implantation approaches.
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| 9. |
- Li, Jiantong, 1980-, et al.
(författare)
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Photodetectors Based on Emerging Materials
- 2023
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Ingår i: Springer Handbook of Semiconductor Devices. - Cham : Springer Nature. ; , s. 777-805
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Bokkapitel (refereegranskat)abstract
- Photodetectors that convert light into electrical signals have become an indispensable element for a large number of technologies to enable extensive applications, ranging from optical communications to advanced imaging and motion detection, to automotive industry particularly including self-driving cars, and to astronomy and space exploration under harsh environment. The present photodetector market is predominated by silicon (CMOS-based) photodetectors. With the continuous growth of application areas, highly desired are photodetectors of higher performance in terms of speed, efficiency, detectable wavelength range, and integrability with semiconductor technology. These necessitate the development of new photodetectors based on special materials, rather than the conventional silicon single crystals, as building blocks for various advanced photodetection platforms. To this end, we summarize in this chapter the recent status of advanced photodetectors based on the emerging material, graphene. Our discussion includes the performance metrics, working mechanisms, practical implementation, as well as opportunities and challenges, for graphene-based photodetectors.
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| 10. |
- Mishukova, Viktoriia
(författare)
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Direct patterning processes for high-performance microsupercapacitors
- 2023
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The surge in miniaturized electronic components driven by the Internet of Things (IoT) has prompted an interest in non-traditional energy storage solutions. For these applications, reduction of size while preserving power and energy densities are of great importance. Within this context, planar microsupercapacitors (MSCs) have emerged as strong candidates for energy storage. Their unique two-dimensional structure, rapid charge-discharge capabilities, high power density, and enduring stability make them highly appealing as power units for on-chip integration.However, the intricate nature of MSC fabrication remains a substantial challenge. Conventionally used indirect patterning processes, such as photolithography, are limiting the implementation of novel functional nanomaterials with high charge storing capacities. As a result, other kinds of direct patterning processes can be used to fabricate state-of-the-art MSCs. Recent studies mainly focused on improving the patterning geometry, minimizing electrode dimensions and narrowing the electrode gap to maintain high resolution of MSCs. However, these efforts were made at the expense of process scalability potential and degree of complexity of the fabrication processes. This thesis aims to develop fabrication process flows with emphasis on simplicity and versatility without sacrificing the possibility for large-scale fabrication of MSCs with high-performance.The first part of this thesis describes the implementation of highly scalable inkjet printing process for fabrication of high-performance MSCs. Typically, inkjet printing can be used to deposit thin films of materials. However, to fabricate MSCs with high-performance, the thickness is a crucial parameter that requires scaling up. The contribution of the first work is dealing with overcoming printing limitations by describing a step-like fabrication process that was developed to overcome the limitations of inkjet printing to increase the thickness of the electrode material, and, therefore its electrochemical performance. The outcome graphene-based solid-state MSCs free from metallic current collector exhibit high areal capacitance of 0.1mF cm−2 and hold promise for on-chip fabrication. In the second work, a facile integration of inkjet printing with an electrodeposition technique is used to fabricate hybrid flexible MSCs based on graphene, Fe2O3, and MnO2 nanomaterials with∼90% capacitance retention after 10 000 charge-discharge cycles.In the second part of this thesis, direct laser writing process is implemented as a viable alternative to fabrication of planar MSCs, based on a variety of highly electrochemically active nanomaterials that are not compatible with inkjet printing. In the third, fourth, and fifth works binder-free ink formulation approaches were developed to fabricate composite nanomaterial films based on graphene, graphene oxide, carbon nanotubes (CNTs), and polyaniline (PANI). Efficient patterning of these films, thanks to the wide range of controls over the laser beam, was realized highlighting the simplicity of the developed fabrication processes for MSCs with high areal capacitance of 172 mF cm−2. Furthermore, it enabled the fabrication of MSCs that can operate in a wide temperature range from 25 to 250 °C.In summary, this thesis reshapes the MSC fabrication process by considering performance, scalability, and process adaptability towards novel functional nanomaterials. These proposed methods are further strengthened by innovative ink formulation strategies using these materials, highlighting their potential applicability in emergent energy storage devices.
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