| 1. |
- Sircova, Anna, et al.
(författare)
-
A global look at time : a 24-country study of the equivalence of the Zimbardo Time Perspective Inventory
- 2014
-
Ingår i: SAGE Open. - : SAGE Publications. - 2158-2440. ; :4, s. 1-12
-
Tidskriftsartikel (refereegranskat)abstract
- In this article, we assess the structural equivalence of the Zimbardo Time Perspective Inventory (ZTPI) across 26 samples from 24 countries (N = 12,200). The ZTPI is proven to be a valid and reliable index of individual differences in time perspective across five temporal categories: Past Negative, Past Positive, Present Fatalistic, Present Hedonistic, and Future. We obtained evidence for invariance of 36 items (out of 56) and also the five-factor structure of ZTPI across 23 countries. The short ZTPI scales are reliable for country-level analysis, whereas we recommend the use of the full scales for individual-level analysis. The short version of ZTPI will further promote integration of research in the time perspective domain in relation to many different psycho-social processes.
|
|
| 2. |
- Anagnostopoulos, I., et al.
(författare)
-
Power-Aware Dynamic Memory Management on Many-Core Platforms Utilizing DVFS
- 2013
-
Ingår i: ACM Transactions on Embedded Computing Systems. - : Association for Computing Machinery (ACM). - 1539-9087 .- 1558-3465. ; 13:1, s. 40-
-
Tidskriftsartikel (refereegranskat)abstract
- Today multicore platforms are already prevalent solutions for modern embedded systems. In the future, embedded platforms will have an even more increased processor core count, composing many-core platforms. In addition, applications are becoming more complex and dynamic and try to efficiently utilize the amount of available resources on the embedded platforms. Efficient memory utilization is a key challenge for application developers, especially since memory is a scarce resource and often becomes the system's bottleneck. To cope with this dynamism and achieve better memory footprint utilization (lowmemory fragmentation) application developers resort to the usage of dynamic memory (heap) management techniques, by allocating and deallocating data at runtime. Moreover, overall power consumption is another key challenge that needs to be taken into consideration. Towards this, designers employ the usage of Dynamic Voltage and Frequency Scaling (DVFS) mechanisms, adapting to the application's computational demands at runtime. In this article, we propose the combination of dynamic memory management techniques with DVFS ones. This is performed by integrating, within thememorymanager, runtimemonitoringmechanisms that steer the DVFSmechanisms to adjust clock frequency and voltage supply based on heap performance. The proposed approach has been evaluated on a distributed shared-memory many-core platform composed of multiple LEON3 processors interconnected by a Network-on-Chip infrastructure, supporting DVFS. Experimental results show that by using the proposed method for monitoring and applying DVFS mechanisms the power consumption concerning dynamic memory management was reduced by approximately 37%. In addition we present the trade-offs the proposed approach. Last, by combining the developed method with heap fragmentation-aware dynamic memory managers, we achieve low heap fragmentation values combined with low power consumption.
|
|
| 3. |
- Siozios, K., et al.
(författare)
-
SPARTAN project : Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications
- 2011
-
Ingår i: 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings. - 9781457706424
-
Konferensbidrag (refereegranskat)abstract
- Vision-based robotic applications exhibit increased computational complexity. This problem becomes even more important regarding mission critical application domains. The SPARTAN project focuses in the tight and optimal implementation of computer vision algorithms targeting to rover navigation for space applications. For evaluation purposes, these algorithms will be implemented with a co-design methodology onto a Virtex-6 FPGA device.
|
|
| 4. |
|
|
