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- Andersson, Stefan, et al.
(författare)
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A Tuned, Inductorless, Recursive Filter LNA in CMOS
- 2002
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Ingår i: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), Florens, Italy, September. ; , s. 351-354
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Konferensbidrag (refereegranskat)abstract
- An active recursive filter approach is proposed for the implementation of an inductorless, tuned LNA in CMOS. Such an LNA was designed and fabricated ina 0.8 μm CMOS process. In simulation, the feasibility of this type of LNA was demonstrated, and reasonably good performance was obtained. The fabricated device shows a center frequency tuning range from 250 MHz to 975 MHz. Gain and Q value are tunable in a wide range. The LNA exhibits an input referred 1 dB compression point of -31 dB m and a noise figure of approximately 3 dB measured at 900 MHz center frequency.
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| 4. |
- Caputa, Peter, et al.
(författare)
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An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
- 2004
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Ingår i: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece. - Berlin, Heidelberg : Springer Berlin/Heidelberg. - 9783540230953 - 9783540302056 ; , s. 849-858
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Konferensbidrag (refereegranskat)abstract
- In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.
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| 5. |
- Caputa, Peter, 1973-
(författare)
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Design of efficient high-speed on-chip global interconnects
- 2004
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The development of integrated circuits is continuously moving towards a System-on Chip realization where global interconnects, connecting circuit blocks separated by a long distance, have been considered a showstopper for process scaling due to their RC-delays. Our knowledge today is that high-speed interconnects must be described by models which include not only R and C, but also inductance and skin effect. One might think that this will make the situation worse, but we show that it is not so.In this thesis, we investigate the relevance of inductance in interconnect models and propose a new scheme for global interconnects based on the utilization of microstrip lines using two upper-level metal layers, one thicker layer for wires and one for a return ground plane. We are concerned with key performance measures such as data delay, maximum data-rate, crosstalk, edge-rates and power dissipation. Using our approach, we show that well-designed, highly lossy, long interconnects may show reasonable delays of the order of twice the delay compared to the velocity of light delay, and allow high data rates disconnected from total delay through wave pipelining. To demonstrate the feasibility of the proposed concept, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over this 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 µm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition energy cost model aimed for efficient power estimation of performance-critical buses. The model, which includes properties that closely capture effects present in high performance VLSI buses, can be used to more accurately determine energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a cache bus architecture used in industry.
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| 10. |
- Svensson, Christer, et al.
(författare)
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High Bandwidth, Low-Latency Global Interconnect
- 2003
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Ingår i: VLSI Circuits and Systems, Proceedings of the SPIE, Vol. 5117, Gran Canaria, Spain, May. - : SPIE. ; , s. 126-134
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320µm wide bus with a capacity of 160Gb/s in a nearly standard 0.18µm process.
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