| 1. |
- Aziz, Abdullah, 1992-, et al.
(författare)
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Distributed Digital Twins as Proxies-Unlocking Composability & Flexibility for Purpose-Oriented Digital Twins
- 2023
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Ingår i: IEEE Access. - : IEEE. - 2169-3536. ; 11, s. 137577-137593
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Tidskriftsartikel (refereegranskat)abstract
- In the realm of Industrial Internet of Things (IoT) and Industrial Cyber-Physical Systems (ICPS), Digital Twins (DTs) have revolutionized the management of physical entities. However, existing implementations often face constraints due to hardware-centric approaches and limited flexibility. This article introduces a transformative paradigm that harnesses the potential of distributed Digital Twins as proxies, enabling software-centricity and unlocking composability and flexibility for purpose-oriented digital twin development and deployment. The proposed microservices-based architecture, rooted in service-oriented architecture (SOA) and microservices principles, emphasizes reusability, modularity, and scalability. Leveraging the Lean Digital Twin Methodology and packaged business capabilities expedites digital twin creation and deployment, facilitating dynamic responses to evolving industrial demands. This architecture segments the industrial realm into physical and virtual spaces, where core components are responsible for digital twin management, deployment, and secure interactions. By abstracting and virtualizing physical entities into individual digital twins, this approach establishes the groundwork for purpose-oriented composite digital twin creation. Our key contributions involve a comprehensive exposition of the architecture, a practical proof-of-concept (PoC) implementation, and the application of the architecture in a use-case scenario. Additionally, we provide an analysis, including a quantitative evaluation of the proxy aspect and a qualitative comparison with traditional approaches. This assessment emphasizes key properties such as reusability, modularity, abstraction, discoverability, and security, transcending the limitations of contemporary industrial systems and enabling agile, adaptable digital proxies to meet modern industrial demands.
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| 2. |
- Panchal, Vaidik, et al.
(författare)
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FPGA implementation of proposed number plate localization algorithm based on YOLOv2 (You Only Look Once)
- 2023
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Ingår i: Microsystem Technologies. - : Springer Nature. - 0946-7076 .- 1432-1858. ; 29:10, s. 1501-1513
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Tidskriftsartikel (refereegranskat)abstract
- Many algorithms used in machine learning and artificial intelligence rely on exact object identification and recognition as their foundation for efficiency and accuracy. Hardware implementation of such methods, when implemented, serves to boost the reliability and productivity of object detection in a wide range of contexts. Hardware implementation of such an algorithm takes a lot of resources and a huge amount of calculation time. The object detection and recognition process require a collection of complex algorithms and a series of filtering approaches to work beyond the boundary conditions. The YOLOv2 network is superior to filters and complicated algorithms for this problem. The authors of this study propose an enhanced YOLOv2 Network for object recognition and a novel approach for optimising the existing YOLOv2 Network for localization to pinpoint the ROI that can be used to scale down and contain the object's original area. The network is proposed by configuring the existing YOLOv2 with additional convolution layers and dropout layers. The dropout layers are added to reduce the dependency on a single neuron and is an effective way of preventing overfitting of the network. Also, instead of ReLU as the activation function, we are using the Swish activation function which tends to provide better results. By isolating and producing the region of interest (ROI) from the original image, the algorithm was able to significantly cut down on both the number of resources needed and the time needed to complete the task. The proposed work is implemented on an FPGA board (Xilinx Zynq-Z7010 FPGA board), and the dataset is collected and prepared by the authors. Data augmentation is done to enhance the training data to enhance the training data, which results in better trained network. MATLAB is used to demonstrate the feasibility of the work and provide a thorough evaluation of its merits. The results show that the accuracy of the conventional algorithm approach drops to 20–30% once you move outside the boundaries, whereas the accuracy of the proposed work increases to 60–70% and a 15–20% increase in efficiency with proposed network based on YOLOv2. The proposed algorithm is three times as fast as the standard method while using only 35 percent as much technology.
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| 3. |
- Sharma, Priyanka, et al.
(författare)
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MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply
- 2023
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Ingår i: Memories - Materials, Devices, Circuits and Systems. - : Elsevier. - 2773-0646. ; 4
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Tidskriftsartikel (refereegranskat)abstract
- The use of Multimedia video content is increased rapidly in the past decade, and most multimedia video content is used by mobile phone users. Multimedia video processing consumes significant power during video compression, and thus low power multimedia video compression is essential for battery operated devices. Moving Picture Experts Group (MPEG) Video encoding is giving a higher compression rate and low bandwidth requirement. Conventional MPEG Video encoding architecture uses the conventional 6T memory cells to store video frames for further compression processing. The failure probability of 6T cells is significantly large (0.0988 at 600 mV supply voltage), leading to a decrease in the output quality of the encoded video. From the hybrid memory matrix formulation, it is calculated that storing higher-order MSB bits in highly stable memory cells will provide high-quality video encoding processing as compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. Hence, in this research work instant of using conventional 6T memory cells during video encoding processing, a unique Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSB’s) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSB’s) are stored in the conventional 6T bit cells for high-quality video encoding processing. This research article also proposes a separate memory peripheral circuitry for hybrid memory architecture for video encoding techniques. In addition, this article proposes a unique architecture for parallel video processing with the use of a hybrid pixel memory array. The failure probability of 6T and 8T at the worst failure corner (FS corner for read and SF corner for write) is simulated for 30000 Monte-Carlo simulations points at 45 nm CMOS technology node using CADENCE EDA tool. For the simulation work here, a standard Common Intermediate Format/Quarter Common Intermediate Format (CIF/QCIF) Coastguard video sample is used and for output quality here average PSNR method is used and simulation work is performed using the MATLAB tool.The worst PSNR for conventional 6T memory array and Hybrid memory array at 600 mV supply voltage shows improvement in worst minimum PSNR as 6.43 dB is calculated. 30% less power consumption to conventional memory architecture.
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