| 1. |
- Cavo, Luis, et al.
(författare)
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Implementation of an area efficient crypto processor for a NB-IoT SoC platform
- 2018
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Ingår i: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018 : NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. - 9781538676561
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Konferensbidrag (refereegranskat)abstract
- This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.
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| 2. |
- Jafri, Syed Mohammad Asad Hassan, et al.
(författare)
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Polymorphic Configuration Architecture for CGRAs
- 2016
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : IEEE. - 1063-8210 .- 1557-9999. ; 24:1, s. 403-407
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Tidskriftsartikel (refereegranskat)abstract
- In the era of platforms hosting multiple applications with arbitrary reconfiguration requirements, static configuration architectures are neither optimal nor desirable. The static reconfiguration architectures either incur excessive overheads or cannot support advanced features (like time-sharing and runtime parallelism). As a solution to this problem, we present a polymorphic configuration architecture (PCA) that provides each application with a configuration infrastructure tailored to its needs.
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| 3. |
- Jeevaraj, Arun, et al.
(författare)
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FPGA based hybrid computing platform for ESS linac simulator
- 2018
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Ingår i: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018 : NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. - 9781538676561
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Konferensbidrag (refereegranskat)abstract
- This paper presents a scalable and high-Throughput hybrid computing platform for the real-Time multi-particle based Linac (Linear accelerator) simulation model to be used at the European Spallation Source (ESS). The multi-particle simulation model with non-linear modeling is needed to provide a realistic behavior of the particle beam for reducing the losses at the superconducting structures. The computation complexity of the simulations can reach 1012 matrix multiplication operations for a test case of 106 beam particles simulated over 106 cells. An OpenCL (Open Computing Language) based framework is used to map the processing intensive parts of the simulation model efficiently to any configuration of a CPU-, GPU-and FPGA-based platform. Optimizations using data precision strategies have also been explored to further improve the throughput after reaching memory access saturation. We are able to achieve up to 89 × speed up compared to a C++ benchmark of the same system.
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| 4. |
- Nunez-Prieto, Ricardo, et al.
(författare)
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A Real-Time Gesture Recognition System with FPGA Accelerated ZynqNet Classification
- 2019
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Ingår i: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. - 9781728127699 - 9781728127705
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Konferensbidrag (refereegranskat)abstract
- This paper presents a real-time hand gesture recognition system by accelerating a convolutional neural network (CNN) using FPGA platform. More specifically, ZynqNet is adopted and modified to fulfill the classification task of recognizing the Swedish manual alphabet, which is used by sign language users for spelling purposes, also known as fingerspelling. Data augmentation and transfer learning techniques have been used during the training phase to improve the classification accuracy up to 80.1%, even with an 8-bit ZynqNet model. Extensive analysis of memory requirements and data processing patterns has been performed to enable optimization techniques, including memory partitioning and register arrays. The resulting FPGA implementation on a Xilinx UltraScale device avoids the use of off-chip memories, which together with block-wise processing scheduling, achieves an image rate of 23.5 frames per second (FPS) at 200 MHz clock frequency.
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| 5. |
- Tan, Siyu, et al.
(författare)
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A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS
- 2019
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Ingår i: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. - 9781728127705 - 9781728127699
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Konferensbidrag (refereegranskat)abstract
- This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.
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