| 1. |
- Eslami Kiasari, Abbas, et al.
(författare)
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A Markovian performance model for networks-on-chip
- 2007
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Ingår i: Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing. - 9780769530895 ; , s. 157-164
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Konferensbidrag (refereegranskat)abstract
- Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Thus, it is of crucial importance for a designer to have access to fast methods for evaluating the performance of on-chip network. To this end, we present a Markovian model for evaluating the latency and energy consumption of on-chip networks, We compute the average delay due to path contention, virtual channel and crossbar switch arbitration using a queuing-based approach, which can capture the blocking phenomena of wormhole switching quite accurately. The model is then used to estimate the power consumption of all routers m NoCs The performance results from the analytical models are validated with those obtained from a synthesizable VHDL-based cycle accurate simulator Comparison with simulation results indicate that the proposed analytical model quite accurate and can be used as an efficient design tool by SoC designers.
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| 2. |
- Eslami Kiasari, Abbas, et al.
(författare)
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PERMAP : A Performance-Aware Mapping for Application-Specific SoCs
- 2008
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Ingår i: 2008 International Conference on Application-Specific Systems, Architectures and Processors. - 9781424418978 ; , s. 73-78
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Konferensbidrag (refereegranskat)abstract
- Future System-on-Chip (SoC) designs will need efficient on-chip communication architectures that can provide efficient and scalable data transport among the Intellectual Properties (IPs). Designing and optimizing SoCs is an increasingly difficult task due to the size and complexity of the SoC design space, high cost of detailed simulation, and several constraints that the design must satisfy. For efficient design of SoCs, an efficient mapping of IPs onto Networks-on-Chip (NoCs) is highly desirable. Towards this end, we have presented PERMAP, a PERformance-aware MAPping algorithm which maps the IPs onto a generic NoC architecture such that the average communication delay is minimized This is accomplished by a performance analytical model which can be used for any arbitrary network topology with wormhole routing, The algorithm is used for mapping a video application onto a tile-based NoC and experimental results show that PERMAP is fast and robust.
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| 3. |
- Rahmati, D., et al.
(författare)
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Power-Efficient Routing Algorithm for Torus NoCs
- 2008
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Ingår i: Proceedings of the International Conference on Contemporary Computing (IC3). ; , s. 211-220
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Konferensbidrag (refereegranskat)abstract
- Modern System-on-Chip (SoC) architectures use Network-on-Chip (NoC) for high-speed internode communication. NoC with torus interconnection topology is now popular due to its low dimension and simple structure. Torus NoC is very similar to the mesh NoC from a structural point of view, but has rather smaller diameter that makes it a suitable choice for NoCs. For a routing algorithm to be deadlock-free in a torus NoC at least two virtual channels should be used to avoid channel dependency, while mesh NoC can handle deadlock freedom using only one virtual channel. In this paper, we propose a novel approach on designing routing algorithms for mesh and torus NoCs. Also a deadlock free routing algorithm is proposed for Torus NoC that uses only one virtual channel per physical channel resulting in lower power consumption because of reduced hardware complexity and with no significant performance degradation. The algorithm works within a dimension and is applied to all dimensions individually for XY routing and various turn based deterministic routing algorithms like west first, north last and negative first. We have proved efficiency of the algorithm using simulation results obtained from synthesis of our implemented VHDL Register Transfer Level (RTL) model of NoC.
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