| 1. |
- Fougstedt, Christoffer, 1990, et al.
(författare)
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ASIC Implementation of Time-Domain Digital Back Propagation for Coherent Receivers
- 2018
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Ingår i: IEEE Photonics Technology Letters. - 1041-1135 .- 1941-0174. ; 30:13, s. 1179-1182
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Tidskriftsartikel (refereegranskat)abstract
- Digital back propagation (DBP) is often proposed and implemented offline for the mitigation of nonlinear impairments in long-haul fiber communications. However, complexity in terms of chip area and power consumption in a realistic application-specific integrated circuit implementation is yet to be determined. Here, we implement time-domain DBP (TD-DBP) in a 28-nm fully-depleted silicon-on-insulator process technology, considering digital implementation aspects such as limited-resolution arithmetic and finite-length filters. We choose as example a coherent optical transmission system, viz. a single-channel, single-polarization, and 20-GBd 16-QAM system, for which the DBP is known to perform well. For the considered system, we find that the TD-DBP can enable a reach increase from 3400 to 5300 km, at a power dissipation of <20 W (or, conversely, an energy dissipation of <230 pJ/bit), at a pre-FEC BER of 10-2.
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| 2. |
- Lundberg, Lars, 1989, et al.
(författare)
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Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels
- 2018
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Ingår i: European Conference on Optical Communication, ECOC. ; 2018-September
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Konferensbidrag (refereegranskat)abstract
- The power consumption of a circuit implementation of a master-slave carrier recovery scheme is studied. Slave power consumption is 27% of master power for 16QAM and 13% for 64QAM, enabling power savings approaching 0.7W per channel through joint processing.
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| 3. |
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| 4. |
- Fougstedt, Christoffer, 1990, et al.
(författare)
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Energy-Efficient High-Throughput Staircase Decoders
- 2018
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Ingår i: Optics InfoBase Conference Papers. - 2162-2701. - 9781557528209 ; , s. 1-3
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Konferensbidrag (refereegranskat)abstract
- We introduce staircase decoder implementations achieving up to 1-Tb/s throughput with energy dissipation of 1.2 pJ/information bit. The implementations are estimated to achieve >10.5 dB of net coding gain depending on the configuration.
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| 5. |
- Fougstedt, Christoffer, 1990, et al.
(författare)
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Filter Implementation for Power-Efficient Chromatic Dispersion Compensation
- 2018
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Ingår i: IEEE Photonics Journal. - 1943-0655. ; 10:4
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Tidskriftsartikel (refereegranskat)abstract
- Chromatic dispersion (CD) compensation in coherent fiber-optic systems represents a very significant DSP block in terms of power dissipation. Since spectrally efficient coherent systems are expected to find a wider deployment in systems shorter than long haul, it becomes relevant to investigate filter implementation aspects of CD compensation in the context of systems with low-to-moderate amounts of accumulated dispersion. The investigation we perform in this paper has an emphasis on implementation aspects such as power dissipation and area usage, it deals with both time-domain and frequency-domain CD compensations, and it considers both A/D-conversion quantization and fixed-point filter design aspects. To enable an accurate analysis on power dissipation and chip area, the evaluated filters are implemented in a 28-nm fully depleted silicon-on-insulator (FD-SOI) process technology. We show that an optimization of the filter response that takes pulse shaping into account can significantly reduce power dissipation and area usage of time-domain implementations, making them a viable alternative to frequency-domain implementations.
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| 6. |
- Fougstedt, Christoffer, 1990
(författare)
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High-Throughput Power-Efficient DSP for Fiber-Optic Communication Systems
- 2018
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Communication networks are a vital backbone of the modern society. Power dissipation of optical communication links and digital signal processing (DSP) subsystems for these links are a major concern as throughput requirements increase, and the number of deployed systems grows. We are approaching fundamental integrated-circuit scaling limits quickly, and it is thus no longer possible to assume that feature-size scaling will enable implementation of ever more complex algorithms. Therefore, approaching DSP from an implementation perspective, and designing low-power high-performance algorithms will become increasingly more important.This thesis considers power- and energy-efficiency improvements in real-time implementation of DSP algorithms. High-throughput parallel implementations of algorithms are presented and improvements in currently-employed major power-dissipating DSP subsystems (chromatic dispersion compensation and dynamic equalization) are considered. Implementation-aware design of advanced algorithms for long-haul transmission systems is considered. This thesis also considers possible power-reduction in short-haul systems through introduction of forward error correction.
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| 7. |
- Larsson-Edefors, Per, 1967, et al.
(författare)
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Implementation Challenges for Energy-Efficient Error Correction in Optical Communication Systems
- 2018
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Ingår i: Optics InfoBase Conference Papers. - 2162-2701. ; Part F112-SPPCom 2018
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Konferensbidrag (refereegranskat)abstract
- We describe energy-efficient hard- and soft-decision forward error correction circuits for optical communication systems. We discuss challenges of implementing circuits that combine high energy efficiency, high throughput, and high net coding gain.
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| 8. |
- Ryman, Erik J, 1982, et al.
(författare)
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Custom versus Cell-Based ASIC Design for Many-Channel Correlators
- 2018
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Ingår i: IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. - 1520-6130. - 9781538663189 ; 2018-October, s. 176-180
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Konferensbidrag (refereegranskat)abstract
- While ASICs are efficient in terms of area utilization, performance, and power dissipation, ASIC design requires significant development resources. We compare two approaches to implementing ASIC correlators for interferometric imagers and spectrometers: The first approach, custom design, gives very high performance and area utilization, but is complex and time consuming. The second approach, cell-based design, reduces design time, but leads to lower performance and area utilization. In our evaluation, we consider two different correlator architectures: Autocorrelators for spectrometry, and cross-correlators for synthetic aperture imaging. Based on both 65-nm CMOS and 28-nm FD-SOI process technologies, our results show that for implementations for a limited number of channels, the cell-based approach may prove useful since it offers relatively short development time while still providing acceptable area utilization and performance. For larger designs, however, the area overhead of cell-based design becomes a major concern, especially for autocorrelator architectures.
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