| 1. |
- Börjeson, Erik, 1984, et al.
(författare)
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ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems
- 2019
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Ingår i: Optics InfoBase Conference Papers. - 2162-2701. - 9781943580538
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Konferensbidrag (refereegranskat)abstract
- We develop circuit implementations and explore design optimizations for one blind and one pilot-based carrier phase-recovery algorithm, where the former algorithm is shown to dissipate 1.8-4.5 pJ/bit and the latter 0.5-0.3 pJ/bit, using 16 to 256QAM.
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| 2. |
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| 3. |
- Fougstedt, Christoffer, 1990
(författare)
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Energy-Efficient Digital Signal Processing for Fiber-Optic Communication Systems
- 2019
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Modern fiber-optic communication systems rely on complex digital signal processing (DSP) and forward error correction (FEC), which contribute to a significant amount of the over-all link power dissipation. Bandwidth demands are evergrowing and circuit technology scaling will due to fundamental reasons come to an end; energy-efficient design of DSP is thus necessary both from a sustainability perspective and a technical perspective. This thesis explores energy-efficient design of the sub-systems that are estimated to contribute to the majority of the receiver application-specific integrated-circuit power dissipation: chromatic-dispersion compensation, dynamic equalization, nonlinearity mitigation, and forward error correction. With a focus on real-time-processing circuit implementation of the considered algorithms, aspects such as finite-precision effects, pipelining, and parallel processing are explored, the impact on compensation and correction performance is investigated, and energy-efficient circuit implementations are developed. The sub-systems are investigated both individually, and in a system context. DSP designs showing significant energy-efficiency improvements are presented, as well as very high-throughput, energy-efficient, FEC designs. The subsystems are also considered in the context of datacenter interconnect links, and it is shown that DSP-based coherent systems are feasible even in power constrained settings.
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| 4. |
- Fougstedt, Christoffer, 1990, et al.
(författare)
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Energy-Efficient High-Throughput VLSI Architectures for Product-Like Codes
- 2019
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Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 37:2, s. 477-485
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Tidskriftsartikel (refereegranskat)abstract
- Implementing forward error correction (FEC) for modern long-haul fiber-optic communication systems is a challenge, since these high-throughput systems require FEC circuits that can combine high coding gains and energy-efficient operation. We present VLSI decoder architectures for product-like codes for systems with strict throughput and power dissipation requirements. To reduce energy dissipation, our architectures are designed to minimize data transfers in and out of memory blocks, and to use parallel non-iterative component decoders. Using a mature 28-nm VLSI process technology node, we showcase different product and staircase decoder implementations that have the capacity to exceed 1-Tb/s information throughputs with energy efficiencies of around 2 pJ/bit.
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| 5. |
- Fougstedt, Christoffer, 1990, et al.
(författare)
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Energy-Efficient Soft-Assisted Product Decoders
- 2019
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Ingår i: 2019 Optical Fiber Communications Conference and Exhibition, OFC 2019 - Proceedings. - 9781943580538
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Konferensbidrag (refereegranskat)abstract
- We implement a 1-Tb/s 0.63-pJ/bit soft-assisted product decoder in a 28-nm technology. The decoder uses one bit of soft information to improve its net coding gain by 0.2 dB, reaching 10.3-10.4 dB, which is similar to that of more complex hard-decision staircase decoders.
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| 6. |
- Jain, Vikram, et al.
(författare)
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Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication
- 2019
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Ingår i: 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. ; , s. 45-48
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Konferensbidrag (refereegranskat)abstract
- Optical communication systems rely on forward error correction (FEC) to decrease the error rate of the received data. Since the properties of the optical channel will vary over time, a variable FEC coding gain would be useful. For example, if the channel conditions are benign, lower code overhead can be used, effectively increasing the code rate. We introduce a variable-rate FEC decoder architecture that can operate in several different modes, where each mode is linked to code rate and decoding iterations. We demonstrate a decoder implementation that provides a net coding gain range of 9.96–10.38 dB at a post-FEC bit-error rate of 10^-15. For this range, a decoder implemented in a 28-nm process technology offers throughputs in excess of 400 Gbps, decoding latencies below 53 ns and a power dissipation of less than 0.95 W (or 1.3 pJ/information bit).
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| 7. |
- Peter, Kenneth, et al.
(författare)
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Hardware considerations for selection networks
- 2019
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Ingår i: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC. - 2324-8440 .- 2324-8432. ; 2019-October, s. 40-45
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Konferensbidrag (refereegranskat)abstract
- The selection operation is a central part of a soft-decision error-correction algorithm, which is important for high-performance communication networks. High symbol rates and power-dissipation limitations motivate hardware implementation as a comparator network. We use industry-standard tools to investigate VLSI hardware implementation of selection networks with up to 512 inputs. We find theoretical network depth and size to be poor predictors of hardware performance. In a 65-nm process, we find that our novel half-life network is competitive with and in some cases superior to Zazon-Ivry’s pairwise and odd/even selection networks, for delay, area, and energy per selection operation.
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